X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2Fyucca.h;h=76717e4579158cc654ca7a2c47ee163581548202;hb=9f6044256ecb3aa2d62f1f26ca564d0e55e19458;hp=0b4dfb8e73f1df0bc839dd8e2ca8893f48524aa6;hpb=2a72e9ed18d2164eb7fe569119342eb631b568da;p=u-boot

diff --git a/include/configs/yucca.h b/include/configs/yucca.h
index 0b4dfb8e73..76717e4579 100644
--- a/include/configs/yucca.h
+++ b/include/configs/yucca.h
@@ -1,23 +1,7 @@
 /*
  * (C) Copyright 2004 Paul Reynolds <PaulReynolds@lhsolutions.com>
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:	GPL-2.0+
  */
 
 /************************************************************************
@@ -34,7 +18,6 @@
 /*-----------------------------------------------------------------------
  * High Level Configuration Options
  *----------------------------------------------------------------------*/
-#define CONFIG_4xx			1	/* ... PPC4xx family	*/
 #define CONFIG_440			1	/* ... PPC440 family	*/
 #define CONFIG_440SPE			1	/* Specifc SPe support	*/
 #define CONFIG_440SPE_REVA		1	/* Support old Rev A.	*/
@@ -45,6 +28,8 @@
 #define EXTCLK_50		50000000
 #define EXTCLK_83		83333333
 
+#define	CONFIG_SYS_TEXT_BASE	0xfffb0000
+
 /*
  * Include common defines/options for all AMCC eval boards
  */
@@ -60,7 +45,6 @@
  * actual resources get mapped (not physical addresses)
  *----------------------------------------------------------------------*/
 #define CONFIG_SYS_FLASH_BASE		0xfff00000	/* start of FLASH	*/
-#define CONFIG_SYS_PERIPHERAL_BASE	0xa0000000	/* internal peripherals	*/
 #define CONFIG_SYS_ISRAM_BASE		0x90000000	/* internal SRAM	*/
 
 #define CONFIG_SYS_PCI_MEMBASE		0x80000000	/* mapped PCI memory	*/
@@ -96,19 +80,16 @@
 #define CONFIG_SYS_TEMP_STACK_OCM	1
 #define CONFIG_SYS_OCM_DATA_ADDR	CONFIG_SYS_ISRAM_BASE
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_ISRAM_BASE	/* Initial RAM address	*/
-#define CONFIG_SYS_INIT_RAM_END	0x2000		/* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE	128		/* num bytes initial data */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2000		/* Size of used area in RAM */
 
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
-#define CONFIG_SYS_POST_WORD_ADDR	(CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_POST_WORD_ADDR
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
 
 /*-----------------------------------------------------------------------
  * Serial Port
  *----------------------------------------------------------------------*/
-#undef CONFIG_UART1_CONSOLE
+#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
 
-#undef	CONFIG_SERIAL_SOFTWARE_FIFO
 #undef CONFIG_SYS_EXT_SERIAL_CLOCK
 /* #define CONFIG_SYS_EXT_SERIAL_CLOCK	(1843200 * 6) */ /* Ext clk @ 11.059 MHz */
 
@@ -122,13 +103,13 @@
 /*-----------------------------------------------------------------------
  * I2C
  *----------------------------------------------------------------------*/
-#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address	*/
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
 
 #define IIC0_BOOTPROM_ADDR	0x50
 #define IIC0_ALT_BOOTPROM_ADDR	0x54
 
 /* Don't probe these addrs */
-#define CONFIG_SYS_I2C_NOPROBES	{0x50, 0x52, 0x53, 0x54}
+#define CONFIG_SYS_I2C_NOPROBES	{ {0, 0x50}, {0, 0x52}, {0, 0x53}, {0, 0x54} }
 
 /* #if defined(CONFIG_CMD_EEPROM) */
 /* #define CONFIG_SYS_I2C_EEPROM_ADDR	0x50 */	/* I2C boot EEPROM		*/
@@ -201,6 +182,7 @@
  */
 /* General PCI */
 #define CONFIG_PCI			/* include pci support		*/
+#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
 #define CONFIG_PCI_PNP		1	/* do pci plug-and-play		*/
 #define CONFIG_PCI_SCAN_SHOW	1	/* show pci devices on startup	*/
 #define CONFIG_PCI_CONFIG_HOST_BRIDGE