X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2Fyucca.h;h=db1d35bdd75f5282d2aef104a8a59ee73edf4046;hb=8d79953d03e6c5b24215609997dafe4daa623cd6;hp=ab323aaab43e67d3b4d2913bf0966dbd36041d77;hpb=dca3b3d6d6396b67e5e84af53452164923c73443;p=u-boot

diff --git a/include/configs/yucca.h b/include/configs/yucca.h
index ab323aaab4..db1d35bdd7 100644
--- a/include/configs/yucca.h
+++ b/include/configs/yucca.h
@@ -46,7 +46,6 @@
 #define EXTCLK_83		83333333
 
 #define	CONFIG_MISC_INIT_F	1	/* Use misc_init_f()		*/
-#define CONFIG_ADD_RAM_INFO	1	/* Print additional info	*/
 #undef  CONFIG_SHOW_BOOT_PROGRESS
 #undef  CONFIG_STRESS
 
@@ -65,15 +64,18 @@
 #define CFG_PCI_TARGBASE	CFG_PCI_MEMBASE
 
 #define CFG_PCIE_MEMBASE	0xb0000000	/* mapped PCIe memory	*/
-#define CFG_PCIE_MEMSIZE	0x01000000
+#define CFG_PCIE_MEMSIZE	0x08000000	/* smallest incr for PCIe port */
 #define CFG_PCIE_BASE		0xe0000000	/* PCIe UTL regs */
 
 #define CFG_PCIE0_CFGBASE	0xc0000000
-#define CFG_PCIE0_XCFGBASE	0xc0000400
-#define CFG_PCIE1_CFGBASE	0xc0001000
-#define CFG_PCIE1_XCFGBASE	0xc0001400
-#define CFG_PCIE2_CFGBASE	0xc0002000
-#define CFG_PCIE2_XCFGBASE	0xc0002400
+#define CFG_PCIE1_CFGBASE	0xc1000000
+#define CFG_PCIE2_CFGBASE	0xc2000000
+#define CFG_PCIE0_XCFGBASE	0xc3000000
+#define CFG_PCIE1_XCFGBASE	0xc3001000
+#define CFG_PCIE2_XCFGBASE	0xc3002000
+
+/* base address of inbound PCIe window */
+#define CFG_PCIE_INBOUND_BASE	0x0000000400000000ULL
 
 /* System RAM mapped to PCI space */
 #define CONFIG_PCI_SYS_MEM_BUS	CFG_SDRAM_BASE
@@ -183,6 +185,8 @@
 		"cp.b ${fileaddr} FFFB0000 ${filesize};"		\
 		"setenv filesize;saveenv\0"				\
 	"upd=run load;run update\0"					\
+	"pciconfighost=1\0"						\
+	"pcie_mode=RP:EP:EP\0"						\
 	""
 #define CONFIG_BOOTCOMMAND	"run flash_self"
 
@@ -192,6 +196,15 @@
 #define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
 
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
 /*
  * Command line configuration.
  */
@@ -289,7 +302,7 @@
 #define CONFIG_PCI			/* include pci support		*/
 #define CONFIG_PCI_PNP		1	/* do pci plug-and-play		*/
 #define CONFIG_PCI_SCAN_SHOW	1	/* show pci devices on startup	*/
-#undef CONFIG_PCI_CONFIG_HOST_BRIDGE
+#define CONFIG_PCI_CONFIG_HOST_BRIDGE
 
 /* Board-specific PCI */
 #define CFG_PCI_TARGET_INIT		/* let board init pci target    */
@@ -311,14 +324,6 @@
  * the maximum mapped by the Linux kernel during initialization.
  */
 #define CFG_BOOTMAPSZ		(8 << 20)	/*Initial Memory map for Linux*/
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE		8192	/* For AMCC 405 CPUs		*/
-#define CFG_CACHELINE_SIZE	32	/* ...				*/
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
-#endif
 
 /*
  * Internal Definitions