X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2Fzipitz2.h;h=afe1e891ddaf415b5c5691d1138e5f946a7d3637;hb=81b1c9ebe1f5a4e36eaccc0e3732c3fbf76f9807;hp=a5a873ba3cff12b75bb2ebbe79f87f426958c3ab;hpb=9efac4a1eb99d9c5539aa6992025eeacab7980c6;p=u-boot

diff --git a/include/configs/zipitz2.h b/include/configs/zipitz2.h
index a5a873ba3c..afe1e891dd 100644
--- a/include/configs/zipitz2.h
+++ b/include/configs/zipitz2.h
@@ -25,11 +25,11 @@
 /*
  * High Level Board Configuration Options
  */
-#define	CONFIG_PXA27X		1	/* Marvell PXA270 CPU */
+#define	CONFIG_CPU_PXA27X		1	/* Marvell PXA270 CPU */
 #define	CONFIG_ZIPITZ2		1	/* Zipit Z2 board */
+#define	CONFIG_SYS_TEXT_BASE	0x0
 
-#undef	BOARD_LATE_INIT
-#undef	CONFIG_SKIP_RELOCATE_UBOOT
+#undef	CONFIG_BOARD_LATE_INIT
 #undef	CONFIG_USE_IRQ
 #undef	CONFIG_SKIP_LOWLEVEL_INIT
 
@@ -41,11 +41,12 @@
 #define CONFIG_ENV_ADDR			0x40000
 #define CONFIG_ENV_SIZE			0x20000
 
-#define	CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + CONFIG_STACKSIZE)
-#define	CONFIG_SYS_GBL_DATA_SIZE	512
+#define	CONFIG_SYS_MALLOC_LEN		(128*1024)
+#define	CONFIG_ARCH_CPU_INIT
 
 #define	CONFIG_BOOTCOMMAND						\
-	"if mmc init && fatload mmc 0 0xa0000000 uboot.script ; then "	\
+	"if mmc rescan && ext2load mmc 0 0xa0000000 boot/uboot.script ;"\
+	"then "								\
 		"source 0xa0000000; "					\
 	"else "								\
 		"bootm 0x60000; "					\
@@ -56,7 +57,7 @@
 #define	CONFIG_BOOTDELAY		2	/* Autoboot delay */
 #define	CONFIG_CMDLINE_TAG
 #define	CONFIG_SETUP_MEMORY_TAGS
-
+#define	CONFIG_SYS_TEXT_BASE		0x0
 #define	CONFIG_LZMA			/* LZMA compression support */
 
 /*
@@ -74,6 +75,7 @@
 #include <config_cmd_default.h>
 
 #undef	CONFIG_CMD_NET
+#undef	CONFIG_CMD_NFS
 #define	CONFIG_CMD_ENV
 #undef	CONFIG_CMD_IMLS
 #define	CONFIG_CMD_MMC
@@ -84,7 +86,8 @@
  */
 #ifdef	CONFIG_CMD_MMC
 #define	CONFIG_MMC
-#define	CONFIG_PXA_MMC
+#define	CONFIG_GENERIC_MMC
+#define	CONFIG_PXA_MMC_GENERIC
 #define	CONFIG_SYS_MMC_BASE		0xF0000000
 #define	CONFIG_CMD_FAT
 #define CONFIG_CMD_EXT2
@@ -160,6 +163,12 @@ unsigned char zipitz2_spi_read(void);
 #define	CONFIG_STACKSIZE_FIQ		(4*1024)	/* FIQ stack */
 #endif
 
+/*
+ * SRAM Map
+ */
+#define	PHYS_SRAM			0x5c000000	/* SRAM Bank #1 */
+#define	PHYS_SRAM_SIZE			0x00040000	/* 256k */
+
 /*
  * DRAM Map
  */
@@ -175,6 +184,9 @@ unsigned char zipitz2_spi_read(void);
 
 #define	CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_DRAM_BASE
 
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define	CONFIG_SYS_INIT_SP_ADDR		(GENERATED_GBL_DATA_SIZE + PHYS_SRAM + 2048)
+
 /*
  * NOR FLASH
  */
@@ -218,7 +230,7 @@ unsigned char zipitz2_spi_read(void);
 #define CONFIG_SYS_GPCR3_VAL	0x00000000
 #define CONFIG_SYS_GPDR0_VAL	0xdafcee00
 #define CONFIG_SYS_GPDR1_VAL	0xffa3aaab
-#define CONFIG_SYS_GPDR2_VAL	0x8fe1ffff
+#define CONFIG_SYS_GPDR2_VAL	0x8fe9ffff
 #define CONFIG_SYS_GPDR3_VAL	0x001b1f8a
 #define CONFIG_SYS_GPSR0_VAL	0x06080400
 #define CONFIG_SYS_GPSR1_VAL	0x007f0000