X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fdwmmc.h;h=bc1d6e3abbceddef5a1826d051ccafd8748e8fda;hb=44ab2d325b79d3ce6123495c5ce52410655a58fb;hp=6aebe96b97bc795b711e51ef33a4d2d5434fca5c;hpb=c6f086ddcbfb47918b82f6a135c61f432540da42;p=u-boot

diff --git a/include/dwmmc.h b/include/dwmmc.h
index 6aebe96b97..bc1d6e3abb 100644
--- a/include/dwmmc.h
+++ b/include/dwmmc.h
@@ -1,8 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * (C) Copyright 2012 SAMSUNG Electronics
  * Jaehoon Chung <jh80.chung@samsung.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #ifndef __DWMMC_HW_H
@@ -105,7 +104,7 @@
 
 /* Status Register */
 #define DWMCI_BUSY		(1 << 9)
-#define DWMCI_FIFO_MASK		0x1ff
+#define DWMCI_FIFO_MASK		0x1fff
 #define DWMCI_FIFO_SHIFT	17
 
 /* FIFOTH Register */
@@ -253,14 +252,12 @@ static inline u8 dwmci_readb(struct dwmci_host *host, int reg)
  * See rockchip_dw_mmc.c for an example.
  *
  * @cfg:	Configuration structure to fill in (generally &plat->mmc)
- * @name:	Device name (normally dev->name)
- * @buswidth:	Bus width (in bits, such as 4 or 8)
- * @caps:	Host capabilities (MMC_MODE_...)
- * @max_clk:	Maximum supported clock speed in HZ (e.g. 400000)
- * @min_clk:	Minimum supported clock speed in HZ (e.g. 150000000)
+ * @host:	DWMMC host
+ * @max_clk:	Maximum supported clock speed in HZ (e.g. 150000000)
+ * @min_clk:	Minimum supported clock speed in HZ (e.g. 400000)
  */
-void dwmci_setup_cfg(struct mmc_config *cfg, const char *name, int buswidth,
-		     uint caps, u32 max_clk, u32 min_clk);
+void dwmci_setup_cfg(struct mmc_config *cfg, struct dwmci_host *host,
+		u32 max_clk, u32 min_clk);
 
 /**
  * dwmci_bind() - Set up a new MMC block device
@@ -286,18 +283,15 @@ int dwmci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg);
  * This is used when you are not using CONFIG_BLK. Convert your driver over!
  *
  * @host:	DWMMC host structure
- * @max_clk:	Maximum supported clock speed in HZ (e.g. 400000)
- * @min_clk:	Minimum supported clock speed in HZ (e.g. 150000000)
+ * @max_clk:	Maximum supported clock speed in HZ (e.g. 150000000)
+ * @min_clk:	Minimum supported clock speed in HZ (e.g. 400000)
  * @return 0 if OK, -ve on error
  */
 int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk);
 #endif /* !CONFIG_BLK */
 
-#ifdef CONFIG_DM_MMC_OPS
+#ifdef CONFIG_DM_MMC
 /* Export the operations to drivers */
-int dwmci_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
-		   struct mmc_data *data);
-int dwmci_set_ios(struct udevice *dev);
 int dwmci_probe(struct udevice *dev);
 extern const struct dm_mmc_ops dm_dwmci_ops;
 #endif