X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Ffsl_nfc.h;h=279aaa55de055a792e150e658dec5e88a4d14bfd;hb=ccf7988b9ace671085a7ae6e7317c6a378c4a309;hp=da5be379d1984113fbe3c173da9249c0ba34957a;hpb=40c642bc19b9fa2906e3172487a522fee456340b;p=u-boot

diff --git a/include/fsl_nfc.h b/include/fsl_nfc.h
index da5be379d1..279aaa55de 100644
--- a/include/fsl_nfc.h
+++ b/include/fsl_nfc.h
@@ -1,5 +1,4 @@
 /*
- *
  * (c) 2009 Magnus Lilja <lilja.magnus@gmail.com>
  *
  * See file CREDITS for list of people who contributed to this
@@ -25,21 +24,57 @@
 #define __FSL_NFC_H
 
 /*
+ * TODO: Use same register defs for nand_spl mxc nand driver
+ * and mtd mxc nand driver.
+ *
  * Register map and bit definitions for the Freescale NAND Flash
- * Controller present in i.MX31 and other devices.
+ * Controller present in various i.MX devices.
+ *
+ * MX31 and MX27 have version 1 which has
+ * 	4 512 byte main buffers and
+ * 	4 16 byte spare buffers
+ * 	to support up to 2K byte pagesize nand.
+ * 	Reading or writing a 2K page requires 4 FDI/FDO cycles.
+ *
+ * MX25 has version 1.1 which has
+ * 	8 512 byte main buffers and
+ * 	8 64 byte spare buffers
+ * 	to support up to 4K byte pagesize nand.
+ * 	Reading or writing a 2K or 4K page requires only 1 FDI/FDO cycle.
+ *      Also some of registers are moved and/or changed meaning as seen below.
  */
+#if defined(CONFIG_MX31) || defined(CONFIG_MX27)
+#define MXC_NFC_V1
+#elif defined(CONFIG_MX25)
+#define MXC_NFC_V1_1
+#else
+#warning "MXC NFC version not defined"
+#endif
+
+#if defined(MXC_NFC_V1)
+#define NAND_MXC_NR_BUFS		4
+#define NAND_MXC_SPARE_BUF_SIZE		16
+#define NAND_MXC_REG_OFFSET		0xe00
+#define NAND_MXC_2K_MULTI_CYCLE		1
+#elif defined(MXC_NFC_V1_1)
+#define NAND_MXC_NR_BUFS		8
+#define NAND_MXC_SPARE_BUF_SIZE		64
+#define NAND_MXC_REG_OFFSET		0x1e00
+#else
+#error "define CONFIG_NAND_MXC_VXXX to use the mxc spl_nand driver"
+#endif
 
 struct fsl_nfc_regs {
-	u32 main_area0[128]; /* @0x000 */
-	u32 main_area1[128];
-	u32 main_area2[128];
-	u32 main_area3[128];
-	u32 spare_area0[4];
-	u32 spare_area1[4];
-	u32 spare_area2[4];
-	u32 spare_area3[4];
-	u32 reserved1[64 - 16 + 64 * 5];
-	u16 bufsiz; /* @ 0xe00 */
+	u32 main_area[NAND_MXC_NR_BUFS][512/4];
+	u32 spare_area[NAND_MXC_NR_BUFS][NAND_MXC_SPARE_BUF_SIZE/4];
+	/*
+	 * reserved size is offset of nfc registers
+	 * minus total main and spare sizes
+	 */
+	u8 reserved1[NAND_MXC_REG_OFFSET
+		- NAND_MXC_NR_BUFS * (512 + NAND_MXC_SPARE_BUF_SIZE)];
+#if defined(MXC_NFC_V1)
+	u16 bufsiz;
 	u16 reserved2;
 	u16 buffer_address;
 	u16 flash_add;
@@ -54,6 +89,30 @@ struct fsl_nfc_regs {
 	u16 nand_flash_wr_pr_st;
 	u16 nand_flash_config1;
 	u16 nand_flash_config2;
+#elif defined(MXC_NFC_V1_1)
+	u16 reserved2[2];
+	u16 buffer_address;
+	u16 flash_add;
+	u16 flash_cmd;
+	u16 configuration;
+	u16 ecc_status_result;
+	u16 ecc_status_result2;
+	u16 spare_area_size;
+	u16 nf_wr_prot;
+	u16 reserved3[2];
+	u16 nand_flash_wr_pr_st;
+	u16 nand_flash_config1;
+	u16 nand_flash_config2;
+	u16 reserved4;
+	u16 unlock_start_blk_add0;
+	u16 unlock_end_blk_add0;
+	u16 unlock_start_blk_add1;
+	u16 unlock_end_blk_add1;
+	u16 unlock_start_blk_add2;
+	u16 unlock_end_blk_add2;
+	u16 unlock_start_blk_add3;
+	u16 unlock_end_blk_add3;
+#endif
 };
 
 /*
@@ -98,6 +157,9 @@ struct fsl_nfc_regs {
  */
 #define NFC_INT		0x8000
 
+#ifdef MXC_NFC_V1_1
+#define NFC_4_8N_ECC	(1 << 0)
+#endif
 #define NFC_SP_EN	(1 << 2)
 #define NFC_ECC_EN	(1 << 3)
 #define NFC_INT_MSK	(1 << 4)