X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Ffsl_sec.h;h=16e3fcb5a1fdfc59d143101d24ca972d870dac87;hb=07252f6f7e37e23cb43245dcddf8ea8f1d45dec1;hp=e6080d4ff078a4afb592a59c74f0d3d797fa98a5;hpb=4d6647ab17ab9d33c60f7a9f07576c5fbdf6336f;p=u-boot

diff --git a/include/fsl_sec.h b/include/fsl_sec.h
index e6080d4ff0..16e3fcb5a1 100644
--- a/include/fsl_sec.h
+++ b/include/fsl_sec.h
@@ -1,9 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Common internal memory map for some Freescale SoCs
  *
  * Copyright 2014 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #ifndef __FSL_SEC_H
@@ -24,7 +23,7 @@
 #define sec_in16(a)       in_be16(a)
 #define sec_clrbits32     clrbits_be32
 #define sec_setbits32     setbits_be32
-#else
+#elif defined(CONFIG_SYS_FSL_HAS_SEC)
 #error Neither CONFIG_SYS_FSL_SEC_LE nor CONFIG_SYS_FSL_SEC_BE is defined
 #endif
 
@@ -67,6 +66,9 @@ struct rng4tst {
 	};
 	u32 rsvd1[40];
 #define RNG_STATE0_HANDLE_INSTANTIATED	0x00000001
+#define RNG_STATE1_HANDLE_INSTANTIATED	0x00000002
+#define RNG_STATE_HANDLE_MASK	\
+	(RNG_STATE0_HANDLE_INSTANTIATED | RNG_STATE1_HANDLE_INSTANTIATED)
 	u32 rdsta;		/*RNG DRNG Status Register*/
 	u32 rsvd2[15];
 };
@@ -215,6 +217,8 @@ struct sg_entry {
 #define SG_ENTRY_OFFSET_SHIFT	0
 };
 
+#define BLOB_SIZE(x)		((x) + 32 + 16) /* Blob buffer size */
+
 #if defined(CONFIG_MX6) || defined(CONFIG_MX7)
 /* Job Ring Base Address */
 #define JR_BASE_ADDR(x) (CONFIG_SYS_FSL_SEC_ADDR + 0x1000 * (x + 1))
@@ -274,8 +278,6 @@ struct sg_entry {
 #define PERM			0x0000B008      /* Clear on release, lock SMAP
 						 * lock SMAG group 1 Blob */
 
-#define BLOB_SIZE(x)       (x + 32 + 16) /* Blob buffer size */
-
 /* HAB WRAPPED KEY header */
 #define WRP_HDR_SIZE		0x08
 #define HDR_TAG			0x81