X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fgdsys_fpga.h;h=1758d7445ee6d151d3ce1db317e89f42c8c77b20;hb=6eaeba23ddc5ccde5c97ef919ffcbf44ecad73dd;hp=b02e28c8ee49ccc031c0defc1e0e2f07c0428b65;hpb=52158e361606fffca89136481db720fdaab608d0;p=u-boot

diff --git a/include/gdsys_fpga.h b/include/gdsys_fpga.h
index b02e28c8ee..1758d7445e 100644
--- a/include/gdsys_fpga.h
+++ b/include/gdsys_fpga.h
@@ -24,28 +24,31 @@
 #ifndef __GDSYS_FPGA_H
 #define __GDSYS_FPGA_H
 
+int init_func_fpga(void);
+
 enum {
 	FPGA_STATE_DONE_FAILED = 1 << 0,
 	FPGA_STATE_REFLECTION_FAILED = 1 << 1,
+	FPGA_STATE_PLATFORM = 1 << 2,
 };
 
 int get_fpga_state(unsigned dev);
 void print_fpga_state(unsigned dev);
 
-typedef struct ihs_gpio {
+struct ihs_gpio {
 	u16 read;
 	u16 clear;
 	u16 set;
-} ihs_gpio_t;
+};
 
-typedef struct ihs_i2c {
+struct ihs_i2c {
 	u16 write_mailbox;
 	u16 write_mailbox_ext;
 	u16 read_mailbox;
 	u16 read_mailbox_ext;
-} ihs_i2c_t;
+};
 
-typedef struct ihs_osd {
+struct ihs_osd {
 	u16 version;
 	u16 features;
 	u16 control;
@@ -53,10 +56,21 @@ typedef struct ihs_osd {
 	u16 xy_scale;
 	u16 x_pos;
 	u16 y_pos;
-} ihs_osd_t;
+};
+
+#ifdef CONFIG_NEO
+struct ihs_fpga {
+	u16 reflection_low;	/* 0x0000 */
+	u16 versions;		/* 0x0002 */
+	u16 fpga_features;	/* 0x0004 */
+	u16 fpga_version;	/* 0x0006 */
+	u16 reserved_0[8187];	/* 0x0008 */
+	u16 reflection_high;	/* 0x3ffe */
+};
+#endif
 
 #ifdef CONFIG_IO
-typedef struct ihs_fpga {
+struct ihs_fpga {
 	u16 reflection_low;	/* 0x0000 */
 	u16 versions;		/* 0x0002 */
 	u16 fpga_features;	/* 0x0004 */
@@ -65,30 +79,49 @@ typedef struct ihs_fpga {
 	u16 quad_serdes_reset;	/* 0x0012 */
 	u16 reserved_1[8181];	/* 0x0014 */
 	u16 reflection_high;	/* 0x3ffe */
-} ihs_fpga_t;
+};
+#endif
+
+#ifdef CONFIG_IO64
+struct ihs_fpga {
+	u16 reflection_low;	/* 0x0000 */
+	u16 versions;		/* 0x0002 */
+	u16 fpga_features;	/* 0x0004 */
+	u16 fpga_version;	/* 0x0006 */
+	u16 reserved_0[5];	/* 0x0008 */
+	u16 quad_serdes_reset;	/* 0x0012 */
+	u16 reserved_1[502];	/* 0x0014 */
+	u16 ch0_status_int;	/* 0x0400 */
+	u16 ch0_config_int;	/* 0x0402 */
+	u16 reserved_2[126];	/* 0x0404 */
+	u16 ch0_hicb_status_int;/* 0x0500 */
+	u16 ch0_hicb_config_int;/* 0x0502 */
+	u16 reserved_3[7549];	/* 0x0504 */
+	u16 reflection_high;	/* 0x3ffe */
+};
 #endif
 
 #ifdef CONFIG_IOCON
-typedef struct ihs_fpga {
+struct ihs_fpga {
 	u16 reflection_low;	/* 0x0000 */
 	u16 versions;		/* 0x0002 */
 	u16 fpga_version;	/* 0x0004 */
 	u16 fpga_features;	/* 0x0006 */
 	u16 reserved_0[6];	/* 0x0008 */
-	ihs_gpio_t gpio;	/* 0x0014 */
+	struct ihs_gpio gpio;	/* 0x0014 */
 	u16 mpc3w_control;	/* 0x001a */
 	u16 reserved_1[19];	/* 0x001c */
 	u16 videocontrol;	/* 0x0042 */
 	u16 reserved_2[93];	/* 0x0044 */
 	u16 reflection_high;	/* 0x00fe */
-	ihs_osd_t osd;		/* 0x0100 */
-	u16 reserved_3[88];	/* 0x010e */
+	struct ihs_osd osd;	/* 0x0100 */
+	u16 reserved_3[889];	/* 0x010e */
 	u16 videomem;		/* 0x0800 */
-} ihs_fpga_t;
+};
 #endif
 
 #ifdef CONFIG_DLVISION_10G
-typedef struct ihs_fpga {
+struct ihs_fpga {
 	u16 reflection_low;	/* 0x0000 */
 	u16 versions;		/* 0x0002 */
 	u16 fpga_version;	/* 0x0004 */
@@ -96,14 +129,16 @@ typedef struct ihs_fpga {
 	u16 reserved_0[10];	/* 0x0008 */
 	u16 extended_interrupt; /* 0x001c */
 	u16 reserved_1[9];	/* 0x001e */
-	ihs_i2c_t i2c;		/* 0x0030 */
-	u16 reserved_2[51];	/* 0x0038 */
+	struct ihs_i2c i2c;	/* 0x0030 */
+	u16 reserved_2[16];	/* 0x0038 */
+	u16 mpc3w_control;	/* 0x0058 */
+	u16 reserved_3[34];	/* 0x005a */
 	u16 videocontrol;	/* 0x009e */
-	u16 reserved_3[176];	/* 0x00a0 */
-	ihs_osd_t osd;		/* 0x0200 */
-	u16 reserved_4[761];	/* 0x020e */
+	u16 reserved_4[176];	/* 0x00a0 */
+	struct ihs_osd osd;	/* 0x0200 */
+	u16 reserved_5[761];	/* 0x020e */
 	u16 videomem;		/* 0x0800 */
-} ihs_fpga_t;
+};
 #endif
 
 #endif