X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fmpc8220.h;h=c4900a0f1103c37100645b88099f3c813abb2516;hb=834a45d7ee81ef185cc834b44b2dae7b637631e2;hp=fe22b8e5c86a97d43ebe0a59a9945e024ce6e390;hpb=983fda8391fa0ccfd4e0fd0bfb5a5e662e07b222;p=u-boot diff --git a/include/mpc8220.h b/include/mpc8220.h index fe22b8e5c8..c4900a0f11 100644 --- a/include/mpc8220.h +++ b/include/mpc8220.h @@ -35,40 +35,41 @@ /* Exception offsets (PowerPC standard) */ #define EXC_OFF_SYS_RESET 0x0100 +#define _START_OFFSET EXC_OFF_SYS_RESET /* Internal memory map */ /* MPC8220 Internal Register MMAP */ -#define MMAP_MBAR (CFG_MBAR + 0x00000000) /* chip selects */ -#define MMAP_MEMCTL (CFG_MBAR + 0x00000100) /* sdram controller */ -#define MMAP_XLBARB (CFG_MBAR + 0x00000200) /* xlb arbitration control */ -#define MMAP_CDM (CFG_MBAR + 0x00000300) /* clock distribution module */ -#define MMAP_VDOPLL (CFG_MBAR + 0x00000400) /* video PLL */ -#define MMAP_FB (CFG_MBAR + 0x00000500) /* flex bus controller */ -#define MMAP_PCFG (CFG_MBAR + 0x00000600) /* port config */ -#define MMAP_ICTL (CFG_MBAR + 0x00000700) /* interrupt controller */ -#define MMAP_GPTMR (CFG_MBAR + 0x00000800) /* general purpose timers */ -#define MMAP_SLTMR (CFG_MBAR + 0x00000900) /* slice timers */ -#define MMAP_GPIO (CFG_MBAR + 0x00000A00) /* gpio module */ -#define MMAP_XCPCI (CFG_MBAR + 0x00000B00) /* pci controller */ -#define MMAP_PCIARB (CFG_MBAR + 0x00000C00) /* pci arbiter */ -#define MMAP_EXTDMA1 (CFG_MBAR + 0x00000D00) /* external dma1 */ -#define MMAP_EXTDMA2 (CFG_MBAR + 0x00000E00) /* external dma1 */ -#define MMAP_USBH (CFG_MBAR + 0x00001000) /* usb host */ -#define MMAP_CMTMR (CFG_MBAR + 0x00007f00) /* comm timers */ -#define MMAP_DMA (CFG_MBAR + 0x00008000) /* dma */ -#define MMAP_USBD (CFG_MBAR + 0x00008200) /* usb device */ -#define MMAP_COMMPCI (CFG_MBAR + 0x00008400) /* pci comm Bus regs */ -#define MMAP_1284 (CFG_MBAR + 0x00008500) /* 1284 */ -#define MMAP_PEV (CFG_MBAR + 0x00008600) /* print engine video */ -#define MMAP_PSC1 (CFG_MBAR + 0x00008800) /* psc1 block */ -#define MMAP_I2C (CFG_MBAR + 0x00008f00) /* i2c controller */ -#define MMAP_FEC1 (CFG_MBAR + 0x00009000) /* fast ethernet 1 */ -#define MMAP_FEC2 (CFG_MBAR + 0x00009800) /* fast ethernet 2 */ -#define MMAP_JBIGRAM (CFG_MBAR + 0x0000a000) /* jbig RAM */ -#define MMAP_JBIG (CFG_MBAR + 0x0000c000) /* jbig */ -#define MMAP_PDLA (CFG_MBAR + 0x00010000) /* */ -#define MMAP_SRAMCFG (CFG_MBAR + 0x0001ff00) /* SRAM config */ -#define MMAP_SRAM (CFG_MBAR + 0x00020000) /* SRAM */ +#define MMAP_MBAR (CONFIG_SYS_MBAR + 0x00000000) /* chip selects */ +#define MMAP_MEMCTL (CONFIG_SYS_MBAR + 0x00000100) /* sdram controller */ +#define MMAP_XLBARB (CONFIG_SYS_MBAR + 0x00000200) /* xlb arbitration control */ +#define MMAP_CDM (CONFIG_SYS_MBAR + 0x00000300) /* clock distribution module */ +#define MMAP_VDOPLL (CONFIG_SYS_MBAR + 0x00000400) /* video PLL */ +#define MMAP_FB (CONFIG_SYS_MBAR + 0x00000500) /* flex bus controller */ +#define MMAP_PCFG (CONFIG_SYS_MBAR + 0x00000600) /* port config */ +#define MMAP_ICTL (CONFIG_SYS_MBAR + 0x00000700) /* interrupt controller */ +#define MMAP_GPTMR (CONFIG_SYS_MBAR + 0x00000800) /* general purpose timers */ +#define MMAP_SLTMR (CONFIG_SYS_MBAR + 0x00000900) /* slice timers */ +#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x00000A00) /* gpio module */ +#define MMAP_XCPCI (CONFIG_SYS_MBAR + 0x00000B00) /* pci controller */ +#define MMAP_PCIARB (CONFIG_SYS_MBAR + 0x00000C00) /* pci arbiter */ +#define MMAP_EXTDMA1 (CONFIG_SYS_MBAR + 0x00000D00) /* external dma1 */ +#define MMAP_EXTDMA2 (CONFIG_SYS_MBAR + 0x00000E00) /* external dma1 */ +#define MMAP_USBH (CONFIG_SYS_MBAR + 0x00001000) /* usb host */ +#define MMAP_CMTMR (CONFIG_SYS_MBAR + 0x00007f00) /* comm timers */ +#define MMAP_DMA (CONFIG_SYS_MBAR + 0x00008000) /* dma */ +#define MMAP_USBD (CONFIG_SYS_MBAR + 0x00008200) /* usb device */ +#define MMAP_COMMPCI (CONFIG_SYS_MBAR + 0x00008400) /* pci comm Bus regs */ +#define MMAP_1284 (CONFIG_SYS_MBAR + 0x00008500) /* 1284 */ +#define MMAP_PEV (CONFIG_SYS_MBAR + 0x00008600) /* print engine video */ +#define MMAP_PSC1 (CONFIG_SYS_MBAR + 0x00008800) /* psc1 block */ +#define MMAP_I2C (CONFIG_SYS_MBAR + 0x00008f00) /* i2c controller */ +#define MMAP_FEC1 (CONFIG_SYS_MBAR + 0x00009000) /* fast ethernet 1 */ +#define MMAP_FEC2 (CONFIG_SYS_MBAR + 0x00009800) /* fast ethernet 2 */ +#define MMAP_JBIGRAM (CONFIG_SYS_MBAR + 0x0000a000) /* jbig RAM */ +#define MMAP_JBIG (CONFIG_SYS_MBAR + 0x0000c000) /* jbig */ +#define MMAP_PDLA (CONFIG_SYS_MBAR + 0x00010000) /* */ +#define MMAP_SRAMCFG (CONFIG_SYS_MBAR + 0x0001ff00) /* SRAM config */ +#define MMAP_SRAM (CONFIG_SYS_MBAR + 0x00020000) /* SRAM */ #define SRAM_SIZE 0x8000 /* 32 KB */ @@ -258,6 +259,12 @@ /* equates for tx FIFO last write frame pointer reg */ #define PSC_TFLWFPTR(x) (x&0x1ff) /* last write frame pointer */ +/* PCI configuration (only for PLL determination)*/ +#define PCI_REG_PCIGSCR (MMAP_XCPCI + 0x60) /* Global status/control register */ +#define PCI_REG_PCIGSCR_PCI2XLB_CLK_MASK 0x07000000 +#define PCI_REG_PCIGSCR_PCI2XLB_CLK_BIT 24 + +#define PCI_REG_PCICAR (MMAP_XCPCI + 0xF8) /* Configuration Address Register */ /* ------------------------------------------------------------------------ */ /* @@ -294,20 +301,23 @@ /* * Port configuration */ -#define CFG_FEC1_PORT0_CONFIG 0x00000000 -#define CFG_FEC1_PORT1_CONFIG 0x00000000 -#define CFG_1284_PORT0_CONFIG 0x55555557 -#define CFG_1284_PORT1_CONFIG 0x80000000 -#define CFG_FEC2_PORT2_CONFIG 0x00000000 -#define CFG_PEV_PORT2_CONFIG 0x55555540 -#define CFG_GP0_PORT0_CONFIG 0xaaaaaaa0 -#define CFG_GP1_PORT2_CONFIG 0xaaaaa000 -#define CFG_PSC_PORT3_CONFIG 0x00000000 -#define CFG_CS2_PORT3_CONFIG 0x10000000 -#define CFG_CS3_PORT3_CONFIG 0x40000000 -#define CFG_CS4_PORT3_CONFIG 0x00000400 -#define CFG_CS5_PORT3_CONFIG 0x00000100 -#define CFG_I2C_PORT3_CONFIG 0x003c0000 +#define CONFIG_SYS_FEC1_PORT0_CONFIG 0x00000000 +#define CONFIG_SYS_FEC1_PORT1_CONFIG 0x00000000 +#define CONFIG_SYS_1284_PORT0_CONFIG 0x00000000 +#define CONFIG_SYS_1284_PORT1_CONFIG 0x00000000 +#define CONFIG_SYS_FEC2_PORT2_CONFIG 0x00000000 +#define CONFIG_SYS_PEV_PORT2_CONFIG 0x00000000 +#define CONFIG_SYS_GP0_PORT0_CONFIG 0x00000000 +#define CONFIG_SYS_GP1_PORT2_CONFIG 0xaaaaaac0 +#define CONFIG_SYS_PSC_PORT3_CONFIG 0x00020000 +#define CONFIG_SYS_CS1_PORT3_CONFIG 0x00000000 +#define CONFIG_SYS_CS2_PORT3_CONFIG 0x10000000 +#define CONFIG_SYS_CS3_PORT3_CONFIG 0x40000000 +#define CONFIG_SYS_CS4_PORT3_CONFIG 0x00000400 +#define CONFIG_SYS_CS5_PORT3_CONFIG 0x00000200 +#define CONFIG_SYS_PCI_PORT3_CONFIG 0x01400180 +#define CONFIG_SYS_I2C_PORT3_CONFIG 0x00000000 +#define CONFIG_SYS_GP2_PORT3_CONFIG 0x000200a0 /* ------------------------------------------------------------------------ */ /* @@ -523,6 +533,162 @@ struct mpc8220_dma { u32 EU37; /* DMA + 0xfc */ }; +/* + * PCI Header Registers + */ +typedef struct mpc8220_xcpci { + u32 dev_ven_id; /* 0xb00 - device/vendor ID */ + u32 stat_cmd_reg; /* 0xb04 - status command register */ + u32 class_code_rev_id; /* 0xb08 - class code / revision ID */ + u32 bist_htyp_lat_cshl; /* 0xb0c - BIST/HeaderType/Latency/cache line */ + u32 base0; /* 0xb10 - base address 0 */ + u32 base1; /* 0xb14 - base address 1 */ + u32 reserved1[4]; /* 0xb18->0xd27 - base address 2 - 5 */ + u32 cis; /* 0xb28 - cardBus CIS pointer */ + u32 sub_sys_ven_id; /* 0xb2c - sub system ID/ subsystem vendor ID */ + u32 reserved2; /* 0xb30 - expansion ROM base address */ + u32 reserved3; /* 0xb00 - reserved */ + u32 reserved4; /* 0xb00 - reserved */ + u32 mlat_mgnt_ipl; /* 0xb3c - MaxLat/MinGnt/ int pin/int line */ + u32 reserved5[8]; + /* MPC8220 specific - not accessible in PCI header space externally */ + u32 glb_stat_ctl; /* 0xb60 - Global Status Control */ + u32 target_bar0; /* 0xb64 - Target Base Address 0 */ + u32 target_bar1; /* 0xb68 - Target Base Address 1 */ + u32 target_ctrl; /* 0xb6c - Target Control */ + u32 init_win0; /* 0xb70 - Initiator Window 0 Base/Translation */ + u32 init_win1; /* 0xb74 - Initiator Window 1 Base/Translation */ + u32 init_win2; /* 0xb78 - Initiator Window 2 Base/Translation */ + u32 reserved6; /* 0xb7c - reserved */ + u32 init_win_cfg; /* 0xb80 */ + u32 init_ctrl; /* 0xb84 */ + u32 init_stat; /* 0xb88 */ + u32 reserved7[27]; + u32 cfg_adr; /* 0xbf8 */ + u32 reserved8; +} mpc8220_xcpci_t; + +/* PCI->XLB space translation (MPC8220 target), reg0 can address max 256MB, + reg1 - 1GB */ +#define PCI_BASE_ADDR_REG0 0x40000000 +#define PCI_BASE_ADDR_REG1 (CONFIG_SYS_SDRAM_BASE) +#define PCI_TARGET_BASE_ADDR_REG0 (CONFIG_SYS_MBAR) +#define PCI_TARGET_BASE_ADDR_REG1 (CONFIG_SYS_SDRAM_BASE) +#define PCI_TARGET_BASE_ADDR_EN 1<<0 + + +/* PCI Global Status/Control Register (PCIGSCR) */ +#define PCI_GLB_STAT_CTRL_PE_SHIFT 29 +#define PCI_GLB_STAT_CTRL_SE_SHIFT 28 +#define PCI_GLB_STAT_CTRL_XLB_TO_PCI_CLK_SHIFT 24 +#define PCI_GLB_STAT_CTRL_XLB_TO_PCI_CLK_MASK 0x7 +#define PCI_GLB_STAT_CTRL_IPG_TO_PCI_CLK_SHIFT 16 +#define PCI_GLB_STAT_CTRL_IPG_TO_PCI_CLK_MASK 0x7 +#define PCI_GLB_STAT_CTRL_PEE_SHIFT 13 +#define PCI_GLB_STAT_CTRL_SEE_SHIFT 12 +#define PCI_GLB_STAT_CTRL_PR_SHIFT 0 + +#define PCI_GLB_STAT_CTRL_PE (1<