X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fmpc8260.h;h=052529409a159c061f4b23a2fb463f005a2448ad;hb=4f2e92c11f6e2392fc8187829211a5ca7f0c1e12;hp=0462cad8088e9fd593ff5ba39aa9691c1a268324;hpb=1f04521773dfcb9364b95efb3fb0870457a67ee8;p=u-boot

diff --git a/include/mpc8260.h b/include/mpc8260.h
index 0462cad808..052529409a 100644
--- a/include/mpc8260.h
+++ b/include/mpc8260.h
@@ -24,17 +24,36 @@
 /*
  * mpc8260.h
  *
- * MPC8260 specific definitions
+ * MPC8255 / MPC8260 specific definitions
  */
 
 #ifndef __MPC8260_H__
 #define __MPC8260_H__
 
+#ifdef CONFIG_MPC8255
+#define CPU_ID_STR	"MPC8255"
+#endif
+#ifndef CPU_ID_STR
+#if defined(CONFIG_MPC8272_FAMILY)
+#ifdef CONFIG_MPC8247
+#define CPU_ID_STR	"MPC8247"
+#elif defined CONFIG_MPC8248
+#define CPU_ID_STR	"MPC8248"
+#elif defined CONFIG_MPC8271
+#define CPU_ID_STR	"MPC8271"
+#else
+#define CPU_ID_STR	"MPC8272"
+#endif
+#else
+#define CPU_ID_STR	"MPC8260"
+#endif
+#endif /* !CPU_ID_STR */
+
 /*-----------------------------------------------------------------------
  * Exception offsets (PowerPC standard)
  */
 #define EXC_OFF_SYS_RESET	0x0100	/* System reset			*/
-
+#define _START_OFFSET		EXC_OFF_SYS_RESET
 
 /*-----------------------------------------------------------------------
  * BCR - Bus Configuration Register					 4-25
@@ -55,6 +74,7 @@
 #define BCR_EXDD	0x00000400	/* External Master Delay Disable*/
 #define BCR_ISPS	0x00000010	/* Internal Space Port Size	*/
 
+
 /*-----------------------------------------------------------------------
  * PPC_ACR - 60x Bus Arbiter Configuration Register			 4-28
  */
@@ -157,6 +177,7 @@
 #define SIUMCR_MMR10	0x00008000	/* - " -			*/
 #define SIUMCR_MMR11	0x0000c000	/* - " -			*/
 #define SIUMCR_LPBSE	0x00002000	/* LocalBus Parity Byte Select Enable*/
+#define SIUMCR_ABE	0x00000400	/* Address output buffer impedance*/
 
 /*-----------------------------------------------------------------------
  * IMMR - Internal Memory Map Register					 4-34
@@ -281,6 +302,10 @@
 /*-----------------------------------------------------------------------
  * SCCR - System Clock Control Register					 9-8
  */
+#define SCCR_PCI_MODE	0x00000100	/* PCI Mode	*/
+#define SCCR_PCI_MODCK	0x00000080	/* Value of PCI_MODCK pin	*/
+#define SCCR_PCIDF_MSK	0x00000078	/* PCI division factor	*/
+#define SCCR_PCIDF_SHIFT 3
 #define SCCR_CLPD	0x00000004	/* CPM Low Power Disable	*/
 #define SCCR_DFBRG_MSK	0x00000003	/* Division factor of BRGCLK Mask */
 #define SCCR_DFBRG_SHIFT 0
@@ -293,14 +318,15 @@
 /*-----------------------------------------------------------------------
  * SCMR - System Clock Mode Register					 9-9
  */
-#define SCMR_CORECNF_MSK 0x1f000000	/* Core Configuration Mask	*/
+#define SCMR_CORECNF_MSK   0x1f000000	/* Core Configuration Mask	*/
 #define SCMR_CORECNF_SHIFT 24
-#define SCMR_BUSDF_MSK	0x00f00000	/* 60x Bus Division Factor Mask	*/
-#define SCMR_BUSDF_SHIFT 20
-#define SCMR_CPMDF_MSK	0x000f0000	/* CPM Division Factor Mask	*/
-#define SCMR_CPMDF_SHIFT 16
-#define SCMR_PLLDF	0x00001000	/* PLL Pre-divider Value	*/
-#define SCMR_PLLMF_MSK	0x00000fff	/* PLL Multiplication Factor Mask*/
+#define SCMR_BUSDF_MSK	   0x00f00000	/* 60x Bus Division Factor Mask	*/
+#define SCMR_BUSDF_SHIFT   20
+#define SCMR_CPMDF_MSK	   0x000f0000	/* CPM Division Factor Mask	*/
+#define SCMR_CPMDF_SHIFT   16
+#define SCMR_PLLDF	   0x00001000	/* PLL Pre-divider Value	*/
+#define SCMR_PLLMF_MSK	   0x00000fff	/* PLL Multiplication Factor Mask*/
+#define SCMR_PLLMF_MSKH7   0x0000000f	/* for HiP7 processors */
 #define SCMR_PLLMF_SHIFT 0
 
 
@@ -638,7 +664,7 @@
 #define PSDMR_CL_3	     0x00000003	/* CAS Latency = 3		*/
 
 /*-----------------------------------------------------------------------
- * LSDMR - Local Bus SDRAM Mode Register			 	10-24
+ * LSDMR - Local Bus SDRAM Mode Register				10-24
  */
 
 /*
@@ -681,23 +707,23 @@
 /*-----------------------------------------------------------------------
  * TMR1-TMR4 - Timer Mode Registers					17-6
  */
-#define TMRx_PS_MSK		0xff00	/* Prescaler Value 		*/
+#define TMRx_PS_MSK		0xff00	/* Prescaler Value		*/
 #define TMRx_CE_MSK		0x00c0	/* Capture Edge and Enable Interrupt*/
-#define TMRx_OM			0x0020	/* Output Mode 			*/
+#define TMRx_OM			0x0020	/* Output Mode			*/
 #define TMRx_ORI		0x0010	/* Output Reference Interrupt Enable*/
-#define TMRx_FRR		0x0008	/* Free Run/Restart 		*/
+#define TMRx_FRR		0x0008	/* Free Run/Restart		*/
 #define TMRx_ICLK_MSK		0x0006	/* Timer Input Clock Source mask */
-#define TMRx_GE			0x0001	/* Gate Enable  		*/
+#define TMRx_GE			0x0001	/* Gate Enable			*/
 
 #define TMRx_CE_INTR_DIS	0x0000	/* Disable Interrupt on capture event*/
 #define TMRx_CE_RISING		0x0040	/* Capture on Rising TINx edge only */
 #define TMRx_CE_FALLING		0x0080	/* Capture on Falling TINx edge only */
-#define TMRx_CE_ANY		0x00c0	/* Capture on any TINx edge 	*/
+#define TMRx_CE_ANY		0x00c0	/* Capture on any TINx edge	*/
 
-#define TMRx_ICLK_IN_CAS	0x0000	/* Internally cascaded input 	*/
+#define TMRx_ICLK_IN_CAS	0x0000	/* Internally cascaded input	*/
 #define TMRx_ICLK_IN_GEN	0x0002	/* Internal General system clock*/
 #define TMRx_ICLK_IN_GEN_DIV16	0x0004	/* Internal General system clk div 16*/
-#define TMRx_ICLK_TIN_PIN	0x0006	/* TINx pin 			*/
+#define TMRx_ICLK_TIN_PIN	0x0006	/* TINx pin			*/
 
 
 /*-----------------------------------------------------------------------