X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fmpc83xx.h;h=fd742c7809d493660c362bcfdc148024851502c1;hb=18304f7675e84252965b4e24cba279071f1da472;hp=df052e3d4c73fe2dcb62f13b5e5c7762e33a9e9d;hpb=8f00731818f0f0deaca899bde56de98d3d95c0b6;p=u-boot diff --git a/include/mpc83xx.h b/include/mpc83xx.h index df052e3d4c..fd742c7809 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -14,6 +14,7 @@ #define __MPC83XX_H__ #include +#include #if defined(CONFIG_E300) #include #endif @@ -29,7 +30,9 @@ /* IMMRBAR - Internal Memory Register Base Address */ +#ifndef CONFIG_DEFAULT_IMMR #define CONFIG_DEFAULT_IMMR 0xFF400000 /* Default IMMR base address */ +#endif #define IMMRBAR 0x0000 /* Register offset to immr */ #define IMMRBAR_BASE_ADDR 0xFFF00000 /* Base address mask */ #define IMMRBAR_RES ~(IMMRBAR_BASE_ADDR) @@ -48,71 +51,41 @@ /* SPRIDR - System Part and Revision ID Register */ -#define SPRIDR_PARTID 0xFFFF0000 /* Part Identification */ -#define SPRIDR_REVID 0x0000FFFF /* Revision Identification */ - -#define SPR_8349E_REV10 0x80300100 -#define SPR_8349_REV10 0x80310100 -#define SPR_8347E_REV10_TBGA 0x80320100 -#define SPR_8347_REV10_TBGA 0x80330100 -#define SPR_8347E_REV10_PBGA 0x80340100 -#define SPR_8347_REV10_PBGA 0x80350100 -#define SPR_8343E_REV10 0x80360100 -#define SPR_8343_REV10 0x80370100 - -#define SPR_8349E_REV11 0x80300101 -#define SPR_8349_REV11 0x80310101 -#define SPR_8347E_REV11_TBGA 0x80320101 -#define SPR_8347_REV11_TBGA 0x80330101 -#define SPR_8347E_REV11_PBGA 0x80340101 -#define SPR_8347_REV11_PBGA 0x80350101 -#define SPR_8343E_REV11 0x80360101 -#define SPR_8343_REV11 0x80370101 - -#define SPR_8349E_REV31 0x80300300 -#define SPR_8349_REV31 0x80310300 -#define SPR_8347E_REV31_TBGA 0x80320300 -#define SPR_8347_REV31_TBGA 0x80330300 -#define SPR_8347E_REV31_PBGA 0x80340300 -#define SPR_8347_REV31_PBGA 0x80350300 -#define SPR_8343E_REV31 0x80360300 -#define SPR_8343_REV31 0x80370300 - -#define SPR_8360E_REV10 0x80480010 -#define SPR_8360_REV10 0x80490010 -#define SPR_8360E_REV11 0x80480011 -#define SPR_8360_REV11 0x80490011 -#define SPR_8360E_REV12 0x80480012 -#define SPR_8360_REV12 0x80490012 -#define SPR_8360E_REV20 0x80480020 -#define SPR_8360_REV20 0x80490020 -#define SPR_8360E_REV21 0x80480021 -#define SPR_8360_REV21 0x80490021 - -#define SPR_8323E_REV10 0x80620010 -#define SPR_8323_REV10 0x80630010 -#define SPR_8321E_REV10 0x80660010 -#define SPR_8321_REV10 0x80670010 -#define SPR_8323E_REV11 0x80620011 -#define SPR_8323_REV11 0x80630011 -#define SPR_8321E_REV11 0x80660011 -#define SPR_8321_REV11 0x80670011 - -#define SPR_8313E_REV10 0x80B00010 -#define SPR_8313_REV10 0x80B10010 -#define SPR_8311E_REV10 0x80B20010 -#define SPR_8311_REV10 0x80B30010 -#define SPR_8315E_REV10 0x80B40010 -#define SPR_8315_REV10 0x80B50010 -#define SPR_8314E_REV10 0x80B60010 -#define SPR_8314_REV10 0x80B70010 - -#define SPR_8379E_REV10 0x80C20010 -#define SPR_8379_REV10 0x80C30010 -#define SPR_8378E_REV10 0x80C40010 -#define SPR_8378_REV10 0x80C50010 -#define SPR_8377E_REV10 0x80C60010 -#define SPR_8377_REV10 0x80C70010 +#define SPRIDR_PARTID 0xFFFF0000 /* Part Id */ +#define SPRIDR_REVID 0x0000FFFF /* Revision Id */ + +#if defined(CONFIG_MPC834x) +#define REVID_MAJOR(spridr) ((spridr & 0x0000FF00) >> 8) +#define REVID_MINOR(spridr) (spridr & 0x000000FF) +#else +#define REVID_MAJOR(spridr) ((spridr & 0x000000F0) >> 4) +#define REVID_MINOR(spridr) (spridr & 0x0000000F) +#endif + +#define PARTID_NO_E(spridr) ((spridr & 0xFFFE0000) >> 16) +#define SPR_FAMILY(spridr) ((spridr & 0xFFF00000) >> 20) + +#define SPR_831X_FAMILY 0x80B +#define SPR_8311 0x80B2 +#define SPR_8313 0x80B0 +#define SPR_8314 0x80B6 +#define SPR_8315 0x80B4 +#define SPR_832X_FAMILY 0x806 +#define SPR_8321 0x8066 +#define SPR_8323 0x8062 +#define SPR_834X_FAMILY 0x803 +#define SPR_8343 0x8036 +#define SPR_8347_TBGA_ 0x8032 +#define SPR_8347_PBGA_ 0x8034 +#define SPR_8349 0x8030 +#define SPR_836X_FAMILY 0x804 +#define SPR_8358_TBGA_ 0x804A +#define SPR_8358_PBGA_ 0x804E +#define SPR_8360 0x8048 +#define SPR_837X_FAMILY 0x80C +#define SPR_8377 0x80C6 +#define SPR_8378 0x80C4 +#define SPR_8379 0x80C2 /* SPCR - System Priority Configuration Register */ @@ -121,12 +94,13 @@ #define SPCR_PCIPR 0x03000000 /* PCI bridge system bus request priority */ #define SPCR_PCIPR_SHIFT (31-7) #define SPCR_OPT 0x00800000 /* Optimize */ +#define SPCR_OPT_SHIFT (31-8) #define SPCR_TBEN 0x00400000 /* E300 PowerPC core time base unit enable */ #define SPCR_TBEN_SHIFT (31-9) #define SPCR_COREPR 0x00300000 /* E300 PowerPC Core system bus request priority */ #define SPCR_COREPR_SHIFT (31-11) -#if defined(CONFIG_MPC834X) +#if defined(CONFIG_MPC834x) /* SPCR bits - MPC8349 specific */ #define SPCR_TSEC1DP 0x00003000 /* TSEC1 data priority */ #define SPCR_TSEC1DP_SHIFT (31-19) @@ -141,7 +115,7 @@ #define SPCR_TSEC2EP 0x00000003 /* TSEC2 emergency priority */ #define SPCR_TSEC2EP_SHIFT (31-31) -#elif defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X) +#elif defined(CONFIG_MPC831x) || defined(CONFIG_MPC837x) /* SPCR bits - MPC831x and MPC837x specific */ #define SPCR_TSECDP 0x00003000 /* TSEC data priority */ #define SPCR_TSECDP_SHIFT (31-19) @@ -153,7 +127,7 @@ /* SICRL/H - System I/O Configuration Register Low/High */ -#if defined(CONFIG_MPC834X) +#if defined(CONFIG_MPC834x) /* SICRL bits - MPC8349 specific */ #define SICRL_LDP_A 0x80000000 #define SICRL_USB1 0x40000000 @@ -216,8 +190,8 @@ #define SICRH_UC2E1OBI 0x00000002 #define SICRH_UC2E2OBI 0x00000001 -#elif defined(CONFIG_MPC832X) -/* SICRL bits - MPC832X specific */ +#elif defined(CONFIG_MPC832x) +/* SICRL bits - MPC832x specific */ #define SICRL_LDP_LCS_A 0x80000000 #define SICRL_IRQ_CKS 0x20000000 #define SICRL_PCI_MSRC 0x10000000 @@ -288,10 +262,11 @@ #define SICRH_TSOBI1 0x00000002 #define SICRH_TSOBI2 0x00000001 -#elif defined(CONFIG_MPC837X) +#elif defined(CONFIG_MPC837x) /* SICRL bits - MPC837x specific */ #define SICRL_USB_A 0xC0000000 #define SICRL_USB_B 0x30000000 +#define SICRL_USB_B_SD 0x20000000 #define SICRL_UART 0x0C000000 #define SICRL_GPIO_A 0x02000000 #define SICRL_GPIO_B 0x01000000 @@ -333,10 +308,12 @@ #define SICRH_GPIO2_C 0x00002000 #define SICRH_GPIO2_D 0x00001000 #define SICRH_GPIO2_E 0x00000C00 +#define SICRH_GPIO2_E_SD 0x00000800 #define SICRH_GPIO2_F 0x00000300 #define SICRH_GPIO2_G 0x000000C0 #define SICRH_GPIO2_H 0x00000030 #define SICRH_SPI 0x00000003 +#define SICRH_SPI_SD 0x00000001 #endif /* SWCRR - System Watchdog Control Register @@ -376,7 +353,9 @@ /* ATR - Arbiter Timers Register */ #define ATR_DTO 0x00FF0000 /* Data time out */ +#define ATR_DTO_SHIFT 16 #define ATR_ATO 0x000000FF /* Address time out */ +#define ATR_ATO_SHIFT 0 /* AER - Arbiter Event Register */ @@ -390,10 +369,15 @@ /* AEATR - Arbiter Event Address Register */ #define AEATR_EVENT 0x07000000 /* Event type */ +#define AEATR_EVENT_SHIFT 24 #define AEATR_MSTR_ID 0x001F0000 /* Master Id */ +#define AEATR_MSTR_ID_SHIFT 16 #define AEATR_TBST 0x00000800 /* Transfer burst */ +#define AEATR_TBST_SHIFT 11 #define AEATR_TSIZE 0x00000700 /* Transfer Size */ +#define AEATR_TSIZE_SHIFT 8 #define AEATR_TTYPE 0x0000001F /* Transfer Type */ +#define AEATR_TTYPE_SHIFT 0 /* HRCWL - Hard Reset Configuration Word Low */ @@ -440,7 +424,7 @@ #define HRCWL_CORE_TO_CSB_2_5X1 0x00050000 #define HRCWL_CORE_TO_CSB_3X1 0x00060000 -#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X) +#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x) #define HRCWL_CEVCOD 0x000000C0 #define HRCWL_CEVCOD_SHIFT 6 #define HRCWL_CE_PLL_VCO_DIV_4 0x00000000 @@ -494,7 +478,7 @@ #define HRCWL_SVCOD_DIV_8 0x20000000 #define HRCWL_SVCOD_DIV_1 0x30000000 -#elif defined(CONFIG_MPC837X) +#elif defined(CONFIG_MPC837x) #define HRCWL_SVCOD 0x30000000 #define HRCWL_SVCOD_SHIFT 28 #define HRCWL_SVCOD_DIV_4 0x00000000 @@ -509,7 +493,7 @@ #define HRCWH_PCI_HOST_SHIFT 31 #define HRCWH_PCI_AGENT 0x00000000 -#if defined(CONFIG_MPC834X) +#if defined(CONFIG_MPC834x) #define HRCWH_32_BIT_PCI 0x00000000 #define HRCWH_64_BIT_PCI 0x40000000 #endif @@ -520,7 +504,7 @@ #define HRCWH_PCI_ARBITER_DISABLE 0x00000000 #define HRCWH_PCI_ARBITER_ENABLE 0x20000000 -#if defined(CONFIG_MPC834X) +#if defined(CONFIG_MPC834x) #define HRCWH_PCI2_ARBITER_DISABLE 0x00000000 #define HRCWH_PCI2_ARBITER_ENABLE 0x10000000 @@ -544,17 +528,17 @@ #define HRCWH_ROM_LOC_DDR_SDRAM 0x00000000 #define HRCWH_ROM_LOC_PCI1 0x00100000 -#if defined(CONFIG_MPC834X) +#if defined(CONFIG_MPC834x) #define HRCWH_ROM_LOC_PCI2 0x00200000 #endif -#if defined(CONIFG_MPC837X) +#if defined(CONFIG_MPC837x) #define HRCWH_ROM_LOC_ON_CHIP_ROM 0x00300000 #endif #define HRCWH_ROM_LOC_LOCAL_8BIT 0x00500000 #define HRCWH_ROM_LOC_LOCAL_16BIT 0x00600000 #define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000 -#if defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X) +#if defined(CONFIG_MPC831x) || defined(CONFIG_MPC837x) #define HRCWH_ROM_LOC_NAND_SP_8BIT 0x00100000 #define HRCWH_ROM_LOC_NAND_SP_16BIT 0x00200000 #define HRCWH_ROM_LOC_NAND_LP_8BIT 0x00500000 @@ -563,12 +547,14 @@ #define HRCWH_RL_EXT_LEGACY 0x00000000 #define HRCWH_RL_EXT_NAND 0x00040000 +#define HRCWH_TSEC1M_MASK 0x0000E000 #define HRCWH_TSEC1M_IN_MII 0x00000000 #define HRCWH_TSEC1M_IN_RMII 0x00002000 #define HRCWH_TSEC1M_IN_RGMII 0x00006000 #define HRCWH_TSEC1M_IN_RTBI 0x0000A000 #define HRCWH_TSEC1M_IN_SGMII 0x0000C000 +#define HRCWH_TSEC2M_MASK 0x00001C00 #define HRCWH_TSEC2M_IN_MII 0x00000000 #define HRCWH_TSEC2M_IN_RMII 0x00000400 #define HRCWH_TSEC2M_IN_RGMII 0x00000C00 @@ -576,7 +562,7 @@ #define HRCWH_TSEC2M_IN_SGMII 0x00001800 #endif -#if defined(CONFIG_MPC834X) +#if defined(CONFIG_MPC834x) #define HRCWH_TSEC1M_IN_RGMII 0x00000000 #define HRCWH_TSEC1M_IN_RTBI 0x00004000 #define HRCWH_TSEC1M_IN_GMII 0x00008000 @@ -603,7 +589,7 @@ /* RSR - Reset Status Register */ -#if defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X) +#if defined(CONFIG_MPC831x) || defined(CONFIG_MPC837x) #define RSR_RSTSRC 0xF0000000 /* Reset source */ #define RSR_RSTSRC_SHIFT 28 #else @@ -696,7 +682,7 @@ #define SCCR_PCICM 0x00010000 #define SCCR_PCICM_SHIFT 16 -#if defined(CONFIG_MPC834X) +#if defined(CONFIG_MPC834x) /* SCCR bits - MPC834x specific */ #define SCCR_TSEC1CM 0xc0000000 #define SCCR_TSEC1CM_SHIFT 30 @@ -768,9 +754,6 @@ #define SCCR_USBDRCM_2 0x00800000 #define SCCR_USBDRCM_3 0x00c00000 -#define SCCR_PCIEXP1CM 0x00300000 -#define SCCR_PCIEXP2CM 0x000c0000 - #define SCCR_SATA1CM 0x00003000 #define SCCR_SATA1CM_SHIFT 12 #define SCCR_SATACM 0x00003c00 @@ -787,7 +770,7 @@ #define SCCR_TDMCM_2 0x00000020 #define SCCR_TDMCM_3 0x00000030 -#elif defined(CONFIG_MPC837X) +#elif defined(CONFIG_MPC837x) /* SCCR bits - MPC837x specific */ #define SCCR_TSEC1CM 0xc0000000 #define SCCR_TSEC1CM_SHIFT 30 @@ -817,6 +800,17 @@ #define SCCR_USBDRCM_2 0x00800000 #define SCCR_USBDRCM_3 0x00c00000 +/* All of the four SATA controllers must have the same clock ratio */ +#define SCCR_SATA1CM 0x000000c0 +#define SCCR_SATA1CM_SHIFT 6 +#define SCCR_SATACM 0x000000ff +#define SCCR_SATACM_SHIFT 0 +#define SCCR_SATACM_0 0x00000000 +#define SCCR_SATACM_1 0x00000055 +#define SCCR_SATACM_2 0x000000aa +#define SCCR_SATACM_3 0x000000ff +#endif + #define SCCR_PCIEXP1CM 0x00300000 #define SCCR_PCIEXP1CM_SHIFT 20 #define SCCR_PCIEXP1CM_0 0x00000000 @@ -831,17 +825,6 @@ #define SCCR_PCIEXP2CM_2 0x00080000 #define SCCR_PCIEXP2CM_3 0x000c0000 -/* All of the four SATA controllers must have the same clock ratio */ -#define SCCR_SATA1CM 0x000000c0 -#define SCCR_SATA1CM_SHIFT 6 -#define SCCR_SATACM 0x000000ff -#define SCCR_SATACM_SHIFT 0 -#define SCCR_SATACM_0 0x00000000 -#define SCCR_SATACM_1 0x00000055 -#define SCCR_SATACM_2 0x000000aa -#define SCCR_SATACM_3 0x000000ff -#endif - /* CSn_BDNS - Chip Select memory Bounds Register */ #define CSBNDS_SA 0x00FF0000 @@ -854,6 +837,7 @@ #define CSCONFIG_EN 0x80000000 #define CSCONFIG_AP 0x00800000 #define CSCONFIG_ODT_WR_ACS 0x00010000 +#define CSCONFIG_BANK_BIT_3 0x00004000 #define CSCONFIG_ROW_BIT 0x00000700 #define CSCONFIG_ROW_BIT_12 0x00000000 #define CSCONFIG_ROW_BIT_13 0x00000100 @@ -880,7 +864,7 @@ #define TIMING_CFG0_PRE_PD_EXIT_SHIFT 16 #define TIMING_CFG0_ODT_PD_EXIT 0x00000F00 #define TIMING_CFG0_ODT_PD_EXIT_SHIFT 8 -#define TIMING_CFG0_MRS_CYC 0x00000F00 +#define TIMING_CFG0_MRS_CYC 0x0000000F #define TIMING_CFG0_MRS_CYC_SHIFT 0 /* TIMING_CFG_1 - DDR SDRAM Timing Configuration 1 @@ -903,6 +887,11 @@ #define TIMING_CFG1_WRTORD_SHIFT 0 #define TIMING_CFG1_CASLAT_20 0x00030000 /* CAS latency = 2.0 */ #define TIMING_CFG1_CASLAT_25 0x00040000 /* CAS latency = 2.5 */ +#define TIMING_CFG1_CASLAT_30 0x00050000 /* CAS latency = 3.0 */ +#define TIMING_CFG1_CASLAT_35 0x00060000 /* CAS latency = 3.5 */ +#define TIMING_CFG1_CASLAT_40 0x00070000 /* CAS latency = 4.0 */ +#define TIMING_CFG1_CASLAT_45 0x00080000 /* CAS latency = 4.5 */ +#define TIMING_CFG1_CASLAT_50 0x00090000 /* CAS latency = 5.0 */ /* TIMING_CFG_2 - DDR SDRAM Timing Configuration 2 */ @@ -1052,255 +1041,6 @@ #define ECC_ERROR_MAN_SBEC (0xff000000>>24) /* Single Bit Error Counter 0..255 */ #define ECC_ERROR_MAN_SBEC_SHIFT 0 -/* BR - Base Registers - */ -#define BR0 0x5000 /* Register offset to immr */ -#define BR1 0x5008 -#define BR2 0x5010 -#define BR3 0x5018 -#define BR4 0x5020 -#define BR5 0x5028 -#define BR6 0x5030 -#define BR7 0x5038 - -#define BR_BA 0xFFFF8000 -#define BR_BA_SHIFT 15 -#define BR_PS 0x00001800 -#define BR_PS_SHIFT 11 -#define BR_PS_8 0x00000800 /* Port Size 8 bit */ -#define BR_PS_16 0x00001000 /* Port Size 16 bit */ -#define BR_PS_32 0x00001800 /* Port Size 32 bit */ -#define BR_DECC 0x00000600 -#define BR_DECC_SHIFT 9 -#define BR_DECC_OFF 0x00000000 -#define BR_DECC_CHK 0x00000200 -#define BR_DECC_CHK_GEN 0x00000400 -#define BR_WP 0x00000100 -#define BR_WP_SHIFT 8 -#define BR_MSEL 0x000000E0 -#define BR_MSEL_SHIFT 5 -#define BR_MS_GPCM 0x00000000 /* GPCM */ -#define BR_MS_FCM 0x00000020 /* FCM */ -#define BR_MS_SDRAM 0x00000060 /* SDRAM */ -#define BR_MS_UPMA 0x00000080 /* UPMA */ -#define BR_MS_UPMB 0x000000A0 /* UPMB */ -#define BR_MS_UPMC 0x000000C0 /* UPMC */ -#if !defined(CONFIG_MPC834X) -#define BR_ATOM 0x0000000C -#define BR_ATOM_SHIFT 2 -#endif -#define BR_V 0x00000001 -#define BR_V_SHIFT 0 - -#if defined(CONFIG_MPC834X) -#define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_V) -#else -#define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_ATOM | BR_V) -#endif - -/* OR - Option Registers - */ -#define OR0 0x5004 /* Register offset to immr */ -#define OR1 0x500C -#define OR2 0x5014 -#define OR3 0x501C -#define OR4 0x5024 -#define OR5 0x502C -#define OR6 0x5034 -#define OR7 0x503C - -#define OR_GPCM_AM 0xFFFF8000 -#define OR_GPCM_AM_SHIFT 15 -#define OR_GPCM_BCTLD 0x00001000 -#define OR_GPCM_BCTLD_SHIFT 12 -#define OR_GPCM_CSNT 0x00000800 -#define OR_GPCM_CSNT_SHIFT 11 -#define OR_GPCM_ACS 0x00000600 -#define OR_GPCM_ACS_SHIFT 9 -#define OR_GPCM_ACS_0b10 0x00000400 -#define OR_GPCM_ACS_0b11 0x00000600 -#define OR_GPCM_XACS 0x00000100 -#define OR_GPCM_XACS_SHIFT 8 -#define OR_GPCM_SCY 0x000000F0 -#define OR_GPCM_SCY_SHIFT 4 -#define OR_GPCM_SCY_1 0x00000010 -#define OR_GPCM_SCY_2 0x00000020 -#define OR_GPCM_SCY_3 0x00000030 -#define OR_GPCM_SCY_4 0x00000040 -#define OR_GPCM_SCY_5 0x00000050 -#define OR_GPCM_SCY_6 0x00000060 -#define OR_GPCM_SCY_7 0x00000070 -#define OR_GPCM_SCY_8 0x00000080 -#define OR_GPCM_SCY_9 0x00000090 -#define OR_GPCM_SCY_10 0x000000a0 -#define OR_GPCM_SCY_11 0x000000b0 -#define OR_GPCM_SCY_12 0x000000c0 -#define OR_GPCM_SCY_13 0x000000d0 -#define OR_GPCM_SCY_14 0x000000e0 -#define OR_GPCM_SCY_15 0x000000f0 -#define OR_GPCM_SETA 0x00000008 -#define OR_GPCM_SETA_SHIFT 3 -#define OR_GPCM_TRLX 0x00000004 -#define OR_GPCM_TRLX_SHIFT 2 -#define OR_GPCM_EHTR 0x00000002 -#define OR_GPCM_EHTR_SHIFT 1 -#define OR_GPCM_EAD 0x00000001 -#define OR_GPCM_EAD_SHIFT 0 - -#define OR_FCM_AM 0xFFFF8000 -#define OR_FCM_AM_SHIFT 15 -#define OR_FCM_BCTLD 0x00001000 -#define OR_FCM_BCTLD_SHIFT 12 -#define OR_FCM_PGS 0x00000400 -#define OR_FCM_PGS_SHIFT 10 -#define OR_FCM_CSCT 0x00000200 -#define OR_FCM_CSCT_SHIFT 9 -#define OR_FCM_CST 0x00000100 -#define OR_FCM_CST_SHIFT 8 -#define OR_FCM_CHT 0x00000080 -#define OR_FCM_CHT_SHIFT 7 -#define OR_FCM_SCY 0x00000070 -#define OR_FCM_SCY_SHIFT 4 -#define OR_FCM_SCY_1 0x00000010 -#define OR_FCM_SCY_2 0x00000020 -#define OR_FCM_SCY_3 0x00000030 -#define OR_FCM_SCY_4 0x00000040 -#define OR_FCM_SCY_5 0x00000050 -#define OR_FCM_SCY_6 0x00000060 -#define OR_FCM_SCY_7 0x00000070 -#define OR_FCM_RST 0x00000008 -#define OR_FCM_RST_SHIFT 3 -#define OR_FCM_TRLX 0x00000004 -#define OR_FCM_TRLX_SHIFT 2 -#define OR_FCM_EHTR 0x00000002 -#define OR_FCM_EHTR_SHIFT 1 - -#define OR_UPM_AM 0xFFFF8000 -#define OR_UPM_AM_SHIFT 15 -#define OR_UPM_XAM 0x00006000 -#define OR_UPM_XAM_SHIFT 13 -#define OR_UPM_BCTLD 0x00001000 -#define OR_UPM_BCTLD_SHIFT 12 -#define OR_UPM_BI 0x00000100 -#define OR_UPM_BI_SHIFT 8 -#define OR_UPM_TRLX 0x00000004 -#define OR_UPM_TRLX_SHIFT 2 -#define OR_UPM_EHTR 0x00000002 -#define OR_UPM_EHTR_SHIFT 1 -#define OR_UPM_EAD 0x00000001 -#define OR_UPM_EAD_SHIFT 0 - -#define OR_SDRAM_AM 0xFFFF8000 -#define OR_SDRAM_AM_SHIFT 15 -#define OR_SDRAM_XAM 0x00006000 -#define OR_SDRAM_XAM_SHIFT 13 -#define OR_SDRAM_COLS 0x00001C00 -#define OR_SDRAM_COLS_SHIFT 10 -#define OR_SDRAM_ROWS 0x000001C0 -#define OR_SDRAM_ROWS_SHIFT 6 -#define OR_SDRAM_PMSEL 0x00000020 -#define OR_SDRAM_PMSEL_SHIFT 5 -#define OR_SDRAM_EAD 0x00000001 -#define OR_SDRAM_EAD_SHIFT 0 - -#define OR_AM_32KB 0xFFFF8000 -#define OR_AM_64KB 0xFFFF0000 -#define OR_AM_128KB 0xFFFE0000 -#define OR_AM_256KB 0xFFFC0000 -#define OR_AM_512KB 0xFFF80000 -#define OR_AM_1MB 0xFFF00000 -#define OR_AM_2MB 0xFFE00000 -#define OR_AM_4MB 0xFFC00000 -#define OR_AM_8MB 0xFF800000 -#define OR_AM_16MB 0xFF000000 -#define OR_AM_32MB 0xFE000000 -#define OR_AM_64MB 0xFC000000 -#define OR_AM_128MB 0xF8000000 -#define OR_AM_256MB 0xF0000000 -#define OR_AM_512MB 0xE0000000 -#define OR_AM_1GB 0xC0000000 -#define OR_AM_2GB 0x80000000 -#define OR_AM_4GB 0x00000000 - -#define LBLAWAR_EN 0x80000000 -#define LBLAWAR_4KB 0x0000000B -#define LBLAWAR_8KB 0x0000000C -#define LBLAWAR_16KB 0x0000000D -#define LBLAWAR_32KB 0x0000000E -#define LBLAWAR_64KB 0x0000000F -#define LBLAWAR_128KB 0x00000010 -#define LBLAWAR_256KB 0x00000011 -#define LBLAWAR_512KB 0x00000012 -#define LBLAWAR_1MB 0x00000013 -#define LBLAWAR_2MB 0x00000014 -#define LBLAWAR_4MB 0x00000015 -#define LBLAWAR_8MB 0x00000016 -#define LBLAWAR_16MB 0x00000017 -#define LBLAWAR_32MB 0x00000018 -#define LBLAWAR_64MB 0x00000019 -#define LBLAWAR_128MB 0x0000001A -#define LBLAWAR_256MB 0x0000001B -#define LBLAWAR_512MB 0x0000001C -#define LBLAWAR_1GB 0x0000001D -#define LBLAWAR_2GB 0x0000001E - -/* LBCR - Local Bus Configuration Register - */ -#define LBCR_LDIS 0x80000000 -#define LBCR_LDIS_SHIFT 31 -#define LBCR_BCTLC 0x00C00000 -#define LBCR_BCTLC_SHIFT 22 -#define LBCR_LPBSE 0x00020000 -#define LBCR_LPBSE_SHIFT 17 -#define LBCR_EPAR 0x00010000 -#define LBCR_EPAR_SHIFT 16 -#define LBCR_BMT 0x0000FF00 -#define LBCR_BMT_SHIFT 8 - -/* LCRR - Clock Ratio Register - */ -#define LCRR_DBYP 0x80000000 -#define LCRR_DBYP_SHIFT 31 -#define LCRR_BUFCMDC 0x30000000 -#define LCRR_BUFCMDC_SHIFT 28 -#define LCRR_BUFCMDC_1 0x10000000 -#define LCRR_BUFCMDC_2 0x20000000 -#define LCRR_BUFCMDC_3 0x30000000 -#define LCRR_BUFCMDC_4 0x00000000 -#define LCRR_ECL 0x03000000 -#define LCRR_ECL_SHIFT 24 -#define LCRR_ECL_4 0x00000000 -#define LCRR_ECL_5 0x01000000 -#define LCRR_ECL_6 0x02000000 -#define LCRR_ECL_7 0x03000000 -#define LCRR_EADC 0x00030000 -#define LCRR_EADC_SHIFT 16 -#define LCRR_EADC_1 0x00010000 -#define LCRR_EADC_2 0x00020000 -#define LCRR_EADC_3 0x00030000 -#define LCRR_EADC_4 0x00000000 -#define LCRR_CLKDIV 0x0000000F -#define LCRR_CLKDIV_SHIFT 0 -#define LCRR_CLKDIV_2 0x00000002 -#define LCRR_CLKDIV_4 0x00000004 -#define LCRR_CLKDIV_8 0x00000008 - -/* DMAMR - DMA Mode Register - */ -#define DMA_CHANNEL_START 0x00000001 /* Bit - DMAMRn CS */ -#define DMA_CHANNEL_TRANSFER_MODE_DIRECT 0x00000004 /* Bit - DMAMRn CTM */ -#define DMA_CHANNEL_SOURCE_ADRESSS_HOLD_EN 0x00001000 /* Bit - DMAMRn SAHE */ -#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_1B 0x00000000 /* 2Bit- DMAMRn SAHTS 1byte */ -#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_2B 0x00004000 /* 2Bit- DMAMRn SAHTS 2bytes */ -#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_4B 0x00008000 /* 2Bit- DMAMRn SAHTS 4bytes */ -#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_8B 0x0000c000 /* 2Bit- DMAMRn SAHTS 8bytes */ -#define DMA_CHANNEL_SNOOP 0x00010000 /* Bit - DMAMRn DMSEN */ - -/* DMASR - DMA Status Register - */ -#define DMA_CHANNEL_BUSY 0x00000004 /* Bit - DMASRn CB */ -#define DMA_CHANNEL_TRANSFER_ERROR 0x00000080 /* Bit - DMASRn TE */ - /* CONFIG_ADDRESS - PCI Config Address Register */ #define PCI_CONFIG_ADDRESS_EN 0x80000000 @@ -1395,91 +1135,6 @@ */ #define PMCCR1_POWER_OFF 0x00000020 -/* FMR - Flash Mode Register - */ -#define FMR_CWTO 0x0000F000 -#define FMR_CWTO_SHIFT 12 -#define FMR_BOOT 0x00000800 -#define FMR_ECCM 0x00000100 -#define FMR_AL 0x00000030 -#define FMR_AL_SHIFT 4 -#define FMR_OP 0x00000003 -#define FMR_OP_SHIFT 0 - -/* FIR - Flash Instruction Register - */ -#define FIR_OP0 0xF0000000 -#define FIR_OP0_SHIFT 28 -#define FIR_OP1 0x0F000000 -#define FIR_OP1_SHIFT 24 -#define FIR_OP2 0x00F00000 -#define FIR_OP2_SHIFT 20 -#define FIR_OP3 0x000F0000 -#define FIR_OP3_SHIFT 16 -#define FIR_OP4 0x0000F000 -#define FIR_OP4_SHIFT 12 -#define FIR_OP5 0x00000F00 -#define FIR_OP5_SHIFT 8 -#define FIR_OP6 0x000000F0 -#define FIR_OP6_SHIFT 4 -#define FIR_OP7 0x0000000F -#define FIR_OP7_SHIFT 0 -#define FIR_OP_NOP 0x0 /* No operation and end of sequence */ -#define FIR_OP_CA 0x1 /* Issue current column address */ -#define FIR_OP_PA 0x2 /* Issue current block+page address */ -#define FIR_OP_UA 0x3 /* Issue user defined address */ -#define FIR_OP_CM0 0x4 /* Issue command from FCR[CMD0] */ -#define FIR_OP_CM1 0x5 /* Issue command from FCR[CMD1] */ -#define FIR_OP_CM2 0x6 /* Issue command from FCR[CMD2] */ -#define FIR_OP_CM3 0x7 /* Issue command from FCR[CMD3] */ -#define FIR_OP_WB 0x8 /* Write FBCR bytes from FCM buffer */ -#define FIR_OP_WS 0x9 /* Write 1 or 2 bytes from MDR[AS] */ -#define FIR_OP_RB 0xA /* Read FBCR bytes to FCM buffer */ -#define FIR_OP_RS 0xB /* Read 1 or 2 bytes to MDR[AS] */ -#define FIR_OP_CW0 0xC /* Wait then issue FCR[CMD0] */ -#define FIR_OP_CW1 0xD /* Wait then issue FCR[CMD1] */ -#define FIR_OP_RBW 0xE /* Wait then read FBCR bytes */ -#define FIR_OP_RSW 0xF /* Wait then read 1 or 2 bytes */ - -/* FCR - Flash Command Register - */ -#define FCR_CMD0 0xFF000000 -#define FCR_CMD0_SHIFT 24 -#define FCR_CMD1 0x00FF0000 -#define FCR_CMD1_SHIFT 16 -#define FCR_CMD2 0x0000FF00 -#define FCR_CMD2_SHIFT 8 -#define FCR_CMD3 0x000000FF -#define FCR_CMD3_SHIFT 0 - -/* FBAR - Flash Block Address Register - */ -#define FBAR_BLK 0x00FFFFFF - -/* FPAR - Flash Page Address Register - */ -#define FPAR_SP_PI 0x00007C00 -#define FPAR_SP_PI_SHIFT 10 -#define FPAR_SP_MS 0x00000200 -#define FPAR_SP_CI 0x000001FF -#define FPAR_SP_CI_SHIFT 0 -#define FPAR_LP_PI 0x0003F000 -#define FPAR_LP_PI_SHIFT 12 -#define FPAR_LP_MS 0x00000800 -#define FPAR_LP_CI 0x000007FF -#define FPAR_LP_CI_SHIFT 0 - -/* LTESR - Transfer Error Status Register - */ -#define LTESR_BM 0x80000000 -#define LTESR_FCT 0x40000000 -#define LTESR_PAR 0x20000000 -#define LTESR_WP 0x04000000 -#define LTESR_ATMW 0x00800000 -#define LTESR_ATMR 0x00400000 -#define LTESR_CS 0x00080000 -#define LTESR_CC 0x00000001 - /* DDRCDR - DDR Control Driver Register */ #define DDRCDR_DHC_EN 0x80000000 @@ -1501,9 +1156,52 @@ #define DDRCDR_M_ODR 0x00000002 #define DDRCDR_Q_DRN 0x00000001 +/* PCIE Bridge Register +*/ +#define PEX_CSB_CTRL_OBPIOE 0x00000001 +#define PEX_CSB_CTRL_IBPIOE 0x00000002 +#define PEX_CSB_CTRL_WDMAE 0x00000004 +#define PEX_CSB_CTRL_RDMAE 0x00000008 + +#define PEX_CSB_OBCTRL_PIOE 0x00000001 +#define PEX_CSB_OBCTRL_MEMWE 0x00000002 +#define PEX_CSB_OBCTRL_IOWE 0x00000004 +#define PEX_CSB_OBCTRL_CFGWE 0x00000008 + +#define PEX_CSB_IBCTRL_PIOE 0x00000001 + +#define PEX_OWAR_EN 0x00000001 +#define PEX_OWAR_TYPE_CFG 0x00000000 +#define PEX_OWAR_TYPE_IO 0x00000002 +#define PEX_OWAR_TYPE_MEM 0x00000004 +#define PEX_OWAR_RLXO 0x00000008 +#define PEX_OWAR_NANP 0x00000010 +#define PEX_OWAR_SIZE 0xFFFFF000 + +#define PEX_IWAR_EN 0x00000001 +#define PEX_IWAR_TYPE_INT 0x00000000 +#define PEX_IWAR_TYPE_PF 0x00000004 +#define PEX_IWAR_TYPE_NO_PF 0x00000006 +#define PEX_IWAR_NSOV 0x00000008 +#define PEX_IWAR_NSNP 0x00000010 +#define PEX_IWAR_SIZE 0xFFFFF000 +#define PEX_IWAR_SIZE_1M 0x000FF000 +#define PEX_IWAR_SIZE_2M 0x001FF000 +#define PEX_IWAR_SIZE_4M 0x003FF000 +#define PEX_IWAR_SIZE_8M 0x007FF000 +#define PEX_IWAR_SIZE_16M 0x00FFF000 +#define PEX_IWAR_SIZE_32M 0x01FFF000 +#define PEX_IWAR_SIZE_64M 0x03FFF000 +#define PEX_IWAR_SIZE_128M 0x07FFF000 +#define PEX_IWAR_SIZE_256M 0x0FFFF000 + +#define PEX_GCLK_RATIO 0x440 + #ifndef __ASSEMBLY__ struct pci_region; void mpc83xx_pci_init(int num_buses, struct pci_region **reg, int warmboot); +void mpc83xx_pcislave_unlock(int bus); +void mpc83xx_pcie_init(int num_buses, struct pci_region **reg, int warmboot); #endif #endif /* __MPC83XX_H__ */