X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fpci.h;h=1284c427b51a45985118a834f5b79dc29522b123;hb=be662e9a6b7bf27cb7bc06de18f3c51b2ea80160;hp=aaa455434451de8b78a73f56e444656c5d7c90ff;hpb=7fe2a9839423a619b5e232646f93ad915ac2029e;p=u-boot diff --git a/include/pci.h b/include/pci.h index aaa4554344..1284c427b5 100644 --- a/include/pci.h +++ b/include/pci.h @@ -222,6 +222,7 @@ #define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */ #define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */ #define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */ +#define PCI_CAP_ID_EXP 0x10 /* PCI Express */ #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */ #define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */ #define PCI_CAP_SIZEOF 4 @@ -305,6 +306,7 @@ #define PCI_DCR 0x54 /* PCIe Device Control Register */ #define PCI_DSR 0x56 /* PCIe Device Status Register */ #define PCI_LSR 0x5e /* PCIe Link Status Register */ +#define PCI_LCR 0x5c /* PCIe Link Control Register */ #define PCI_LTSSM 0x404 /* PCIe Link Training, Status State Machine */ #define PCI_LTSSM_L0 0x16 /* L0 state */ @@ -419,6 +421,8 @@ struct pci_controller { /* Used by ppc405 autoconfig*/ struct pci_region *pci_fb; int current_busno; + + void *priv_data; }; extern __inline__ void pci_set_ops(struct pci_controller *hose, @@ -510,6 +514,7 @@ extern int pci_hose_write_config_word_via_dword(struct pci_controller *hose, extern void *pci_map_bar(pci_dev_t pdev, int bar, int flags); extern void pci_register_hose(struct pci_controller* hose); extern struct pci_controller* pci_bus_to_hose(int bus); +extern struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr); extern int pci_hose_scan(struct pci_controller *hose); extern int pci_hose_scan_bus(struct pci_controller *hose, int bus); @@ -535,6 +540,7 @@ extern int pci_hose_config_device(struct pci_controller *hose, pci_addr_t mem, unsigned long command); +const char * pci_class_str(u8 class); int pci_last_busno(void); #ifdef CONFIG_MPC824X