X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fpci.h;h=1284c427b51a45985118a834f5b79dc29522b123;hb=ee8fa20f54c9705218a5c21e7db7d4ba1c124b98;hp=c4560060317afbabde345a096298c4f28fb13027;hpb=983eb9d1628a7363f98c8c125522815c429ddf97;p=u-boot

diff --git a/include/pci.h b/include/pci.h
index c456006031..1284c427b5 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -306,6 +306,7 @@
 #define PCI_DCR		0x54    /* PCIe Device Control Register */
 #define PCI_DSR		0x56    /* PCIe Device Status Register */
 #define PCI_LSR		0x5e    /* PCIe Link Status Register */
+#define PCI_LCR		0x5c    /* PCIe Link Control Register */
 #define PCI_LTSSM	0x404   /* PCIe Link Training, Status State Machine */
 #define  PCI_LTSSM_L0	0x16    /* L0 state */
 
@@ -420,6 +421,8 @@ struct pci_controller {
 	/* Used by ppc405 autoconfig*/
 	struct pci_region *pci_fb;
 	int current_busno;
+
+	void *priv_data;
 };
 
 extern __inline__ void pci_set_ops(struct pci_controller *hose,
@@ -511,6 +514,7 @@ extern int pci_hose_write_config_word_via_dword(struct pci_controller *hose,
 extern void *pci_map_bar(pci_dev_t pdev, int bar, int flags);
 extern void pci_register_hose(struct pci_controller* hose);
 extern struct pci_controller* pci_bus_to_hose(int bus);
+extern struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr);
 
 extern int pci_hose_scan(struct pci_controller *hose);
 extern int pci_hose_scan_bus(struct pci_controller *hose, int bus);