X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fpci.h;h=1c8e21688f6303c699133adbede234a57391c136;hb=b99ba1679e8cd51b023e67098c89e606e47137d2;hp=0fc00e42769fd130938b4c2079fd59b4297431c6;hpb=795bee849603c7c2994ba20fcd96f3f9835ffd96;p=u-boot

diff --git a/include/pci.h b/include/pci.h
index 0fc00e4276..1c8e21688f 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -270,6 +270,15 @@
 #define  PCI_AGP_COMMAND_RATE1	0x0001	/* Use 4x rate */
 #define PCI_AGP_SIZEOF		12
 
+/* PCI-X registers */
+
+#define  PCI_X_CMD_DPERR_E      0x0001  /* Data Parity Error Recovery Enable */
+#define  PCI_X_CMD_ERO          0x0002  /* Enable Relaxed Ordering */
+#define  PCI_X_CMD_MAX_READ     0x0000  /* Max Memory Read Byte Count */
+#define  PCI_X_CMD_MAX_SPLIT    0x0030  /* Max Outstanding Split Transactions */
+#define  PCI_X_CMD_VERSION(x)   (((x) >> 12) & 3) /* Version */
+
+
 /* Slot Identification */
 
 #define PCI_SID_ESR		2	/* Expansion Slot Register */
@@ -293,13 +302,19 @@
 #define PCI_MAX_PCI_DEVICES	32
 #define PCI_MAX_PCI_FUNCTIONS	8
 
+#define PCI_DCR		0x54    /* PCIe Device Control Register */
+#define PCI_DSR		0x56    /* PCIe Device Status Register */
+#define PCI_LSR		0x5e    /* PCIe Link Status Register */
+#define PCI_LTSSM	0x404   /* PCIe Link Training, Status State Machine */
+#define  PCI_LTSSM_L0	0x16    /* L0 state */
+
 /* Include the ID list */
 
 #include <pci_ids.h>
 
 struct pci_region {
 	unsigned long bus_start;		/* Start on the bus */
-	unsigned long phys_start;		/* Start in physical address space */
+	phys_addr_t phys_start;			/* Start in physical address space */
 	unsigned long size;			/* Size */
 	unsigned long flags;			/* Resource flags */
 
@@ -316,7 +331,7 @@ struct pci_region {
 
 extern __inline__ void pci_set_region(struct pci_region *reg,
 				      unsigned long bus_start,
-				      unsigned long phys_start,
+				      phys_addr_t phys_start,
 				      unsigned long size,
 				      unsigned long flags) {
 	reg->bus_start	= bus_start;
@@ -417,10 +432,10 @@ extern __inline__ void pci_set_ops(struct pci_controller *hose,
 
 extern void pci_setup_indirect(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data);
 
-extern unsigned long pci_hose_bus_to_phys(struct pci_controller* hose,
-					  unsigned long addr, unsigned long flags);
+extern phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose,
+					unsigned long addr, unsigned long flags);
 extern unsigned long pci_hose_phys_to_bus(struct pci_controller* hose,
-					  unsigned long addr, unsigned long flags);
+					  phys_addr_t addr, unsigned long flags);
 
 #define pci_phys_to_bus(dev, addr, flags) \
 	pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags))
@@ -492,4 +507,7 @@ extern int pci_hose_config_device(struct pci_controller *hose,
 extern void pci_mpc824x_init (struct pci_controller *hose);
 #endif
 
+#ifdef CONFIG_MPC85xx
+extern void pci_mpc85xx_init (struct pci_controller *hose);
+#endif
 #endif	/* _PCI_H */