X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fpci.h;h=7c9a0e344100ecd31aacbde47281c3aaea36b32a;hb=77a318545d57aefa844752465b94c7e09a3f26d0;hp=705d1fcd8a64b44765f2c0101c443efd47312065;hpb=72ed528a948b151e7be5ce03ed3d2b88a229dd0a;p=u-boot

diff --git a/include/pci.h b/include/pci.h
index 705d1fcd8a..7c9a0e3441 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -271,11 +271,14 @@
 #define PCI_AGP_SIZEOF		12
 
 /* PCI-X registers */
-#define  PCI_X_CMD_DPERR_E      0x0001  /* Data Parity Error Recovery Enable */+#define  PCI_X_CMD_ERO          0x0002  /* Enable Relaxed Ordering */
+
+#define  PCI_X_CMD_DPERR_E      0x0001  /* Data Parity Error Recovery Enable */
+#define  PCI_X_CMD_ERO          0x0002  /* Enable Relaxed Ordering */
 #define  PCI_X_CMD_MAX_READ     0x0000  /* Max Memory Read Byte Count */
 #define  PCI_X_CMD_MAX_SPLIT    0x0030  /* Max Outstanding Split Transactions */
 #define  PCI_X_CMD_VERSION(x)   (((x) >> 12) & 3) /* Version */
 
+
 /* Slot Identification */
 
 #define PCI_SID_ESR		2	/* Expansion Slot Register */
@@ -498,4 +501,7 @@ extern int pci_hose_config_device(struct pci_controller *hose,
 extern void pci_mpc824x_init (struct pci_controller *hose);
 #endif
 
+#ifdef CONFIG_MPC85xx
+extern void pci_mpc85xx_init (struct pci_controller *hose);
+#endif
 #endif	/* _PCI_H */