X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fpci.h;h=eba122f8c0e14b48d405e5fd8e55ac607fbf6e08;hb=b04eb342af72d5dbcc29ccd7f3f9475044113361;hp=e80b6bdf5063b7d1acc9c96a52fd0c8235be0064;hpb=e1ccf97c5d7651664d37c0c5aa243874b8851b2d;p=u-boot

diff --git a/include/pci.h b/include/pci.h
index e80b6bdf50..eba122f8c0 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -306,6 +306,7 @@
 #define PCI_DCR		0x54    /* PCIe Device Control Register */
 #define PCI_DSR		0x56    /* PCIe Device Status Register */
 #define PCI_LSR		0x5e    /* PCIe Link Status Register */
+#define PCI_LCR		0x5c    /* PCIe Link Control Register */
 #define PCI_LTSSM	0x404   /* PCIe Link Training, Status State Machine */
 #define  PCI_LTSSM_L0	0x16    /* L0 state */
 
@@ -420,6 +421,8 @@ struct pci_controller {
 	/* Used by ppc405 autoconfig*/
 	struct pci_region *pci_fb;
 	int current_busno;
+
+	void *priv_data;
 };
 
 extern __inline__ void pci_set_ops(struct pci_controller *hose,
@@ -524,7 +527,12 @@ extern void pciauto_setup_device(struct pci_controller *hose,
 				 struct pci_region *mem,
 				 struct pci_region *prefetch,
 				 struct pci_region *io);
-int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
+extern void pciauto_prescan_setup_bridge(struct pci_controller *hose,
+				 pci_dev_t dev, int sub_bus);
+extern void pciauto_postscan_setup_bridge(struct pci_controller *hose,
+				 pci_dev_t dev, int sub_bus);
+extern void pciauto_config_init(struct pci_controller *hose);
+extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
 
 extern pci_dev_t pci_find_device (unsigned int vendor, unsigned int device, int index);
 extern pci_dev_t pci_find_devices (struct pci_device_id *ids, int index);