X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fpower%2Fpfuze100_pmic.h;h=41cb710d78f47e61e6ed25e9f4aa5d94c53d1c7e;hb=9cd37b02a010addfbe6b2ed5b2eacd5bd7e36fb8;hp=57b9ca94afc1204378e62dc009ce0ad27932ad0f;hpb=9bea236b3402a262772b66d055ec6431cbd3ba87;p=u-boot diff --git a/include/power/pfuze100_pmic.h b/include/power/pfuze100_pmic.h index 57b9ca94af..41cb710d78 100644 --- a/include/power/pfuze100_pmic.h +++ b/include/power/pfuze100_pmic.h @@ -8,6 +8,11 @@ #ifndef __PFUZE100_PMIC_H_ #define __PFUZE100_PMIC_H_ +/* Device ID */ +enum {PFUZE100 = 0x10, PFUZE200 = 0x11, PFUZE3000 = 0x30}; + +#define PFUZE100_REGULATOR_DRIVER "pfuze100_regulator" + /* PFUZE100 registers */ enum { PFUZE100_DEVICEID = 0x00, @@ -54,9 +59,16 @@ enum { PFUZE100_VGEN5VOL = 0x70, PFUZE100_VGEN6VOL = 0x71, - PMIC_NUM_OF_REGS = 0x7f, + PFUZE100_NUM_OF_REGS = 0x7f, }; +/* Registor offset based on VOLT register */ +#define PFUZE100_VOL_OFFSET 0 +#define PFUZE100_STBY_OFFSET 1 +#define PFUZE100_OFF_OFFSET 2 +#define PFUZE100_MODE_OFFSET 3 +#define PFUZE100_CONF_OFFSET 4 + /* * Buck Regulators */ @@ -133,6 +145,9 @@ enum { #define SW1x_STBY_MASK 0x3f #define SW1x_OFF_MASK 0x3f +#define SW_MODE_MASK 0xf +#define SW_MODE_SHIFT 0 + #define SW1xCONF_DVSSPEED_MASK 0xc0 #define SW1xCONF_DVSSPEED_2US 0x00 #define SW1xCONF_DVSSPEED_4US 0x40 @@ -181,7 +196,12 @@ enum { #define LDO_VOL_MASK 0xf #define LDO_EN (1 << 4) +#define LDO_MODE_SHIFT 4 +#define LDO_MODE_MASK (1 << 4) +#define LDO_MODE_OFF 0 +#define LDO_MODE_ON 1 +#define VREFDDRCON_EN (1 << 4) /* * Boost Regulator */ @@ -193,11 +213,12 @@ enum { #define SWBST_5_15V 3 #define SWBST_VOL_MASK 0x3 -#define SWBST_MODE_MASK 0x6 -#define SWBST_MODE_OFF (2 << 0) -#define SWBST_MODE_PFM (2 << 1) -#define SWBST_MODE_AUTO (2 << 2) -#define SWBST_MODE_APS (2 << 3) +#define SWBST_MODE_MASK 0xC +#define SWBST_MODE_SHIFT 0x2 +#define SWBST_MODE_OFF 0 +#define SWBST_MODE_PFM 1 +#define SWBST_MODE_AUTO 2 +#define SWBST_MODE_APS 3 /* * Regulator Mode Control