X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fpower%2Fpfuze100_pmic.h;h=41cb710d78f47e61e6ed25e9f4aa5d94c53d1c7e;hb=a61047370d0b73ab886c5863e952695b5ee0d75b;hp=cb1060558a6ae0530c7cd2229240987bf68b5fd5;hpb=430abe1cd721aacc6a715f5e8b9192ea6bee96fc;p=u-boot

diff --git a/include/power/pfuze100_pmic.h b/include/power/pfuze100_pmic.h
index cb1060558a..41cb710d78 100644
--- a/include/power/pfuze100_pmic.h
+++ b/include/power/pfuze100_pmic.h
@@ -8,6 +8,11 @@
 #ifndef __PFUZE100_PMIC_H_
 #define __PFUZE100_PMIC_H_
 
+/* Device ID */
+enum {PFUZE100 = 0x10, PFUZE200 = 0x11, PFUZE3000 = 0x30};
+
+#define PFUZE100_REGULATOR_DRIVER	"pfuze100_regulator"
+
 /* PFUZE100 registers */
 enum {
 	PFUZE100_DEVICEID	= 0x00,
@@ -54,9 +59,16 @@ enum {
 	PFUZE100_VGEN5VOL	= 0x70,
 	PFUZE100_VGEN6VOL	= 0x71,
 
-	PMIC_NUM_OF_REGS	= 0x7f,
+	PFUZE100_NUM_OF_REGS	= 0x7f,
 };
 
+/* Registor offset based on VOLT register */
+#define PFUZE100_VOL_OFFSET	0
+#define PFUZE100_STBY_OFFSET	1
+#define PFUZE100_OFF_OFFSET	2
+#define PFUZE100_MODE_OFFSET	3
+#define PFUZE100_CONF_OFFSET	4
+
 /*
  * Buck Regulators
  */
@@ -133,6 +145,9 @@ enum {
 #define SW1x_STBY_MASK    0x3f
 #define SW1x_OFF_MASK     0x3f
 
+#define SW_MODE_MASK	0xf
+#define SW_MODE_SHIFT	0
+
 #define SW1xCONF_DVSSPEED_MASK 0xc0
 #define SW1xCONF_DVSSPEED_2US  0x00
 #define SW1xCONF_DVSSPEED_4US  0x40
@@ -181,7 +196,12 @@ enum {
 
 #define LDO_VOL_MASK	0xf
 #define LDO_EN		(1 << 4)
+#define LDO_MODE_SHIFT	4
+#define LDO_MODE_MASK	(1 << 4)
+#define LDO_MODE_OFF	0
+#define LDO_MODE_ON	1
 
+#define VREFDDRCON_EN	(1 << 4)
 /*
  * Boost Regulator
  */
@@ -194,10 +214,11 @@ enum {
 
 #define SWBST_VOL_MASK	0x3
 #define SWBST_MODE_MASK	0xC
-#define SWBST_MODE_OFF	(0 << 2)
-#define SWBST_MODE_PFM	(1 << 2)
-#define SWBST_MODE_AUTO	(2 << 2)
-#define SWBST_MODE_APS	(3 << 2)
+#define SWBST_MODE_SHIFT 0x2
+#define SWBST_MODE_OFF	0
+#define SWBST_MODE_PFM	1
+#define SWBST_MODE_AUTO	2
+#define SWBST_MODE_APS	3
 
 /*
  * Regulator Mode Control