X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fppc405.h;h=bc2d051fc789de3b088413ac6ef98668ea4651e5;hb=4638b21f2ebc3781def51e82fb4e425a468f2e49;hp=508c77b14e54f2f1db0e146f140a81fddded1422;hpb=dbcc357166bed20df13450e93a501f30b197efd1;p=u-boot

diff --git a/include/ppc405.h b/include/ppc405.h
index 508c77b14e..bc2d051fc7 100644
--- a/include/ppc405.h
+++ b/include/ppc405.h
@@ -565,25 +565,6 @@
 #define	MAL0_RCBS16	(MAL_DCR_BASE + 0x70) /* RX 16 Channel buffer size */
 #define	MAL0_RCBS24	(MAL_DCR_BASE + 0x78) /* RX 24 Channel buffer size */
 
-/*-----------------------------------------------------------------------------
-| IIC Register Offsets
-'----------------------------------------------------------------------------*/
-#define    IICMDBUF	    0x00
-#define    IICSDBUF	    0x02
-#define    IICLMADR	    0x04
-#define    IICHMADR	    0x05
-#define    IICCNTL	    0x06
-#define    IICMDCNTL	    0x07
-#define    IICSTS	    0x08
-#define    IICEXTSTS	    0x09
-#define    IICLSADR	    0x0A
-#define    IICHSADR	    0x0B
-#define    IIC0_CLKDIV	    0x0C
-#define    IICINTRMSK	    0x0D
-#define    IICXFRCNT	    0x0E
-#define    IICXTCNTLSS	    0x0F
-#define    IICDIRECTCNTL    0x10
-
 /*-----------------------------------------------------------------------------
 | UART Register Offsets
 '----------------------------------------------------------------------------*/