X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fppc440.h;h=1c7f11c4885778813295ac5875fcf906daf14ff9;hb=b24444f1b3ef428b8f85974d23d4edb16e9a046f;hp=e407320a9ef38c2c2e487fe7eff597b941f94de9;hpb=daaba9859b0b94571dc3e45ad0c26e136426b351;p=u-boot diff --git a/include/ppc440.h b/include/ppc440.h index e407320a9e..1c7f11c488 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -533,9 +533,12 @@ #define SDRAM_MCSTAT_MIC_MASK 0x80000000 /* Memory init status mask */ #define SDRAM_MCSTAT_MIC_NOTCOMP 0x00000000 /* Mem init not complete */ #define SDRAM_MCSTAT_MIC_COMP 0x80000000 /* Mem init complete */ -#define SDRAM_MCSTAT_SRMS_MASK 0x80000000 /* Mem self refresh stat mask */ +#define SDRAM_MCSTAT_SRMS_MASK 0x40000000 /* Mem self refresh stat mask */ #define SDRAM_MCSTAT_SRMS_NOT_SF 0x00000000 /* Mem not in self refresh */ -#define SDRAM_MCSTAT_SRMS_SF 0x80000000 /* Mem in self refresh */ +#define SDRAM_MCSTAT_SRMS_SF 0x40000000 /* Mem in self refresh */ +#define SDRAM_MCSTAT_IDLE_MASK 0x20000000 /* Mem self refresh stat mask */ +#define SDRAM_MCSTAT_IDLE_NOT 0x00000000 /* Mem contr not idle */ +#define SDRAM_MCSTAT_IDLE 0x20000000 /* Mem contr idle */ /*-----------------------------------------------------------------------------+ | Memory Controller Options 1 @@ -730,6 +733,7 @@ #define SDRAM_WRDTR_LLWP_1_CYC 0x00000000 #define SDRAM_WRDTR_WTR_MASK 0x0E000000 #define SDRAM_WRDTR_WTR_0_DEG 0x06000000 +#define SDRAM_WRDTR_WTR_90_DEG_ADV 0x04000000 #define SDRAM_WRDTR_WTR_180_DEG_ADV 0x02000000 #define SDRAM_WRDTR_WTR_270_DEG_ADV 0x00000000 @@ -847,6 +851,7 @@ #define pbear 0x20 /* periph bus error addr reg */ #define pbesr 0x21 /* periph bus error status reg */ #define xbcfg 0x23 /* external bus configuration reg */ +#define EBC0_CFG 0x23 /* external bus configuration reg */ #define xbcid 0x24 /* external bus core id reg */ #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ @@ -887,12 +892,14 @@ /* PLB4 Arbiter - PowerPC440EP Pass1 */ #define PLB4_DCR_BASE 0x080 +#define plb4_acr (PLB4_DCR_BASE+0x1) #define plb4_revid (PLB4_DCR_BASE+0x2) -#define plb4_acr (PLB4_DCR_BASE+0x3) #define plb4_besr (PLB4_DCR_BASE+0x4) #define plb4_bearl (PLB4_DCR_BASE+0x6) #define plb4_bearh (PLB4_DCR_BASE+0x7) +#define PLB4_ACR_WRP (0x80000000 >> 7) + /* Nebula PLB4 Arbiter - PowerPC440EP */ #define PLB_ARBITER_BASE 0x80 @@ -1350,26 +1357,26 @@ #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX) #define UIC2_DCR_BASE 0xe0 -#define uic2sr (UIC0_DCR_BASE+0x0) /* UIC2 status-Read Clear */ -#define uic2srs (UIC0_DCR_BASE+0x1) /* UIC2 status-Read Set */ -#define uic2er (UIC0_DCR_BASE+0x2) /* UIC2 enable */ -#define uic2cr (UIC0_DCR_BASE+0x3) /* UIC2 critical */ -#define uic2pr (UIC0_DCR_BASE+0x4) /* UIC2 polarity */ -#define uic2tr (UIC0_DCR_BASE+0x5) /* UIC2 triggering */ -#define uic2msr (UIC0_DCR_BASE+0x6) /* UIC2 masked status */ -#define uic2vr (UIC0_DCR_BASE+0x7) /* UIC2 vector */ -#define uic2vcr (UIC0_DCR_BASE+0x8) /* UIC2 vector configuration */ +#define uic2sr (UIC2_DCR_BASE+0x0) /* UIC2 status-Read Clear */ +#define uic2srs (UIC2_DCR_BASE+0x1) /* UIC2 status-Read Set */ +#define uic2er (UIC2_DCR_BASE+0x2) /* UIC2 enable */ +#define uic2cr (UIC2_DCR_BASE+0x3) /* UIC2 critical */ +#define uic2pr (UIC2_DCR_BASE+0x4) /* UIC2 polarity */ +#define uic2tr (UIC2_DCR_BASE+0x5) /* UIC2 triggering */ +#define uic2msr (UIC2_DCR_BASE+0x6) /* UIC2 masked status */ +#define uic2vr (UIC2_DCR_BASE+0x7) /* UIC2 vector */ +#define uic2vcr (UIC2_DCR_BASE+0x8) /* UIC2 vector configuration */ #define UIC3_DCR_BASE 0xf0 -#define uic3sr (UIC1_DCR_BASE+0x0) /* UIC3 status-Read Clear */ -#define uic3srs (UIC0_DCR_BASE+0x1) /* UIC3 status-Read Set */ -#define uic3er (UIC1_DCR_BASE+0x2) /* UIC3 enable */ -#define uic3cr (UIC1_DCR_BASE+0x3) /* UIC3 critical */ -#define uic3pr (UIC1_DCR_BASE+0x4) /* UIC3 polarity */ -#define uic3tr (UIC1_DCR_BASE+0x5) /* UIC3 triggering */ -#define uic3msr (UIC1_DCR_BASE+0x6) /* UIC3 masked status */ -#define uic3vr (UIC1_DCR_BASE+0x7) /* UIC3 vector */ -#define uic3vcr (UIC1_DCR_BASE+0x8) /* UIC3 vector configuration */ +#define uic3sr (UIC3_DCR_BASE+0x0) /* UIC3 status-Read Clear */ +#define uic3srs (UIC3_DCR_BASE+0x1) /* UIC3 status-Read Set */ +#define uic3er (UIC3_DCR_BASE+0x2) /* UIC3 enable */ +#define uic3cr (UIC3_DCR_BASE+0x3) /* UIC3 critical */ +#define uic3pr (UIC3_DCR_BASE+0x4) /* UIC3 polarity */ +#define uic3tr (UIC3_DCR_BASE+0x5) /* UIC3 triggering */ +#define uic3msr (UIC3_DCR_BASE+0x6) /* UIC3 masked status */ +#define uic3vr (UIC3_DCR_BASE+0x7) /* UIC3 vector */ +#define uic3vcr (UIC3_DCR_BASE+0x8) /* UIC3 vector configuration */ #endif /* CONFIG_440SPE */ #if defined(CONFIG_440GX) @@ -3183,7 +3190,8 @@ #define GPIO0 0 #define GPIO1 1 -#if defined(CONFIG_440GP) +#if defined(CONFIG_440GP) || defined(CONFIG_440GX) || \ + defined(CONFIG_440SP) || defined(CONFIG_440SPE) #define GPIO0_BASE (CFG_PERIPHERAL_BASE+0x00000700) #define GPIO0_OR (GPIO0_BASE+0x0) @@ -3268,6 +3276,8 @@ #define GPIO_IN_SEL 0x40000000 /* GPIO_IN value put in GPIO_ISx for the GPIO nb 0 */ /* For the other GPIO number, you must shift */ +#define GPIO_VAL(gpio) (0x80000000 >> (gpio)) + #ifndef __ASSEMBLY__ typedef enum gpio_select { GPIO_SEL, GPIO_ALT1, GPIO_ALT2, GPIO_ALT3 } gpio_select_t; @@ -3278,32 +3288,31 @@ typedef struct { unsigned long add; /* gpio core base address */ gpio_select_t alt_nb; /* Selected Alternate */ } gpio_param_s; - #endif /* __ASSEMBLY__ */ /* * Macros for accessing the indirect EBC registers */ -#define mtebc(reg, data) mtdcr(ebccfga,reg);mtdcr(ebccfgd,data) -#define mfebc(reg, data) mtdcr(ebccfga,reg);data = mfdcr(ebccfgd) +#define mtebc(reg, data) { mtdcr(ebccfga,reg);mtdcr(ebccfgd,data); } +#define mfebc(reg, data) { mtdcr(ebccfga,reg);data = mfdcr(ebccfgd); } /* * Macros for accessing the indirect SDRAM controller registers */ -#define mtsdram(reg, data) mtdcr(memcfga,reg);mtdcr(memcfgd,data) -#define mfsdram(reg, data) mtdcr(memcfga,reg);data = mfdcr(memcfgd) +#define mtsdram(reg, data) { mtdcr(memcfga,reg);mtdcr(memcfgd,data); } +#define mfsdram(reg, data) { mtdcr(memcfga,reg);data = mfdcr(memcfgd); } /* * Macros for accessing the indirect clocking controller registers */ -#define mtclk(reg, data) mtdcr(clkcfga,reg);mtdcr(clkcfgd,data) -#define mfclk(reg, data) mtdcr(clkcfga,reg);data = mfdcr(clkcfgd) +#define mtclk(reg, data) { mtdcr(clkcfga,reg);mtdcr(clkcfgd,data); } +#define mfclk(reg, data) { mtdcr(clkcfga,reg);data = mfdcr(clkcfgd); } /* * Macros for accessing the sdr controller registers */ -#define mtsdr(reg, data) mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,data) -#define mfsdr(reg, data) mtdcr(sdrcfga,reg);data = mfdcr(sdrcfgd) +#define mtsdr(reg, data) { mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,data); } +#define mfsdr(reg, data) { mtdcr(sdrcfga,reg);data = mfdcr(sdrcfgd); } #ifndef __ASSEMBLY__