X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fppc440.h;h=38809f34b4b351dcaf84a9b7f4a596aaecdd349d;hb=7201cfc4a79c0f55f5ebee73c5a626a49cb53f73;hp=61c937d9f9d3742dbe84f8cdc383d0da0266077b;hpb=f780b83316d9af1f61d71cc88b1917b387b9b995;p=u-boot

diff --git a/include/ppc440.h b/include/ppc440.h
index 61c937d9f9..38809f34b4 100644
--- a/include/ppc440.h
+++ b/include/ppc440.h
@@ -282,7 +282,6 @@
 #define sdr_sdstp3	0x4003
 #endif	/* CONFIG_440GX */
 
-#ifdef CONFIG_440
 /*----------------------------------------------------------------------------+
 | Core Configuration/MMU configuration for 440 (CCR1 for 440x5 only).
 +----------------------------------------------------------------------------*/
@@ -306,7 +305,6 @@
 #define MMUCR_IULXE		0x00400000
 #define MMUCR_STS		0x00100000
 #define MMUCR_STID_MASK		0x000000FF
-#endif /* CONFIG_440 */
 
 #ifdef CONFIG_440SPE
 #undef sdr_sdstp2
@@ -3356,6 +3354,19 @@ typedef struct {
 	unsigned long pciClkSync;             /* PCI clock is synchronous        */
 } PPC440_SYS_INFO;
 
+static inline u32 get_mcsr(void)
+{
+	u32 val;
+
+	asm volatile("mfspr %0, 0x23c" : "=r" (val) :);
+	return val;
+}
+
+static inline void set_mcsr(u32 val)
+{
+	asm volatile("mtspr 0x23c, %0" : "=r" (val) :);
+}
+
 #endif	/* _ASMLANGUAGE */
 
 #define RESET_VECTOR		0xfffffffc