X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fvirtex2.h;h=503df9abaeaa2cc9e2769ecb6c776393d356d9fc;hb=85f87de3132db38143b58bae1805e4d066dc9524;hp=2e9a4f52da3d8d75e1e6b9dadc6fd075af7f00c9;hpb=aaf5e825606a70ddc8fca8e366d8c16a6fd3cc7c;p=u-boot

diff --git a/include/virtex2.h b/include/virtex2.h
index 2e9a4f52da..503df9abae 100644
--- a/include/virtex2.h
+++ b/include/virtex2.h
@@ -11,43 +11,46 @@
 
 #include <xilinx.h>
 
-extern int Virtex2_load(Xilinx_desc *desc, const void *image, size_t size);
-extern int Virtex2_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
-extern int Virtex2_info(Xilinx_desc *desc);
-
 /*
  * Slave SelectMap Implementation function table.
  */
 typedef struct {
-	Xilinx_pre_fn	pre;
-	Xilinx_pgm_fn	pgm;
-	Xilinx_init_fn	init;
-	Xilinx_err_fn	err;
-	Xilinx_done_fn	done;
-	Xilinx_clk_fn	clk;
-	Xilinx_cs_fn	cs;
-	Xilinx_wr_fn	wr;
-	Xilinx_rdata_fn	rdata;
-	Xilinx_wdata_fn	wdata;
-	Xilinx_busy_fn	busy;
-	Xilinx_abort_fn	abort;
-	Xilinx_post_fn	post;
-} Xilinx_Virtex2_Slave_SelectMap_fns;
+	xilinx_pre_fn	pre;
+	xilinx_pgm_fn	pgm;
+	xilinx_init_fn	init;
+	xilinx_err_fn	err;
+	xilinx_done_fn	done;
+	xilinx_clk_fn	clk;
+	xilinx_cs_fn	cs;
+	xilinx_wr_fn	wr;
+	xilinx_rdata_fn	rdata;
+	xilinx_wdata_fn	wdata;
+	xilinx_busy_fn	busy;
+	xilinx_abort_fn	abort;
+	xilinx_post_fn	post;
+} xilinx_virtex2_slave_selectmap_fns;
 
 /* Slave Serial Implementation function table */
 typedef struct {
-	Xilinx_pgm_fn	pgm;
-	Xilinx_clk_fn	clk;
-	Xilinx_rdata_fn	rdata;
-	Xilinx_wdata_fn	wdata;
-} Xilinx_Virtex2_Slave_Serial_fns;
+	xilinx_pgm_fn	pgm;
+	xilinx_clk_fn	clk;
+	xilinx_rdata_fn	rdata;
+	xilinx_wdata_fn	wdata;
+} xilinx_virtex2_slave_serial_fns;
+
+#if defined(CONFIG_FPGA_VIRTEX2)
+extern struct xilinx_fpga_op virtex2_op;
+# define FPGA_VIRTEX2_OPS	&virtex2_op
+#else
+# define FPGA_VIRTEX2_OPS	NULL
+#endif
 
 /* Device Image Sizes (in bytes)
  *********************************************************************/
-#define XILINX_XC2V40_SIZE		(338208 / 8)
-#define XILINX_XC2V80_SIZE		(597408 / 8)
-#define XILINX_XC2V250_SIZE		(1591584 / 8)
-#define XILINX_XC2V500_SIZE		(2557857 / 8)
+#define XILINX_XC2V40_SIZE	(338208 / 8)
+#define XILINX_XC2V80_SIZE	(597408 / 8)
+#define XILINX_XC2V250_SIZE	(1591584 / 8)
+#define XILINX_XC2V500_SIZE	(2557857 / 8)
 #define XILINX_XC2V1000_SIZE	(3749408 / 8)
 #define XILINX_XC2V1500_SIZE	(5166240 / 8)
 #define XILINX_XC2V2000_SIZE	(6808352 / 8)
@@ -60,39 +63,51 @@ typedef struct {
 /* Descriptor Macros
  *********************************************************************/
 #define XILINX_XC2V40_DESC(iface, fn_table, cookie)	\
-{ Xilinx_Virtex2, iface, XILINX_XC2V40_SIZE, fn_table, cookie }
+{ xilinx_virtex2, iface, XILINX_XC2V40_SIZE, fn_table, cookie, \
+	FPGA_VIRTEX2_OPS }
 
 #define XILINX_XC2V80_DESC(iface, fn_table, cookie) \
-{ Xilinx_Virtex2, iface, XILINX_XC2V80_SIZE, fn_table, cookie }
+{ xilinx_virtex2, iface, XILINX_XC2V80_SIZE, fn_table, cookie, \
+	FPGA_VIRTEX2_OPS }
 
 #define XILINX_XC2V250_DESC(iface, fn_table, cookie) \
-{ Xilinx_Virtex2, iface, XILINX_XC2V250_SIZE, fn_table, cookie }
+{ xilinx_virtex2, iface, XILINX_XC2V250_SIZE, fn_table, cookie, \
+	FPGA_VIRTEX2_OPS }
 
 #define XILINX_XC2V500_DESC(iface, fn_table, cookie) \
-{ Xilinx_Virtex2, iface, XILINX_XC2V500_SIZE, fn_table, cookie }
+{ xilinx_virtex2, iface, XILINX_XC2V500_SIZE, fn_table, cookie, \
+	FPGA_VIRTEX2_OPS }
 
 #define XILINX_XC2V1000_DESC(iface, fn_table, cookie) \
-{ Xilinx_Virtex2, iface, XILINX_XC2V1000_SIZE, fn_table, cookie }
+{ xilinx_virtex2, iface, XILINX_XC2V1000_SIZE, fn_table, cookie, \
+	FPGA_VIRTEX2_OPS }
 
 #define XILINX_XC2V1500_DESC(iface, fn_table, cookie) \
-{ Xilinx_Virtex2, iface, XILINX_XC2V1500_SIZE, fn_table, cookie }
+{ xilinx_virtex2, iface, XILINX_XC2V1500_SIZE, fn_table, cookie, \
+	FPGA_VIRTEX2_OPS }
 
 #define XILINX_XC2V2000_DESC(iface, fn_table, cookie) \
-{ Xilinx_Virtex2, iface, XILINX_XC2V2000_SIZE, fn_table, cookie }
+{ xilinx_virtex2, iface, XILINX_XC2V2000_SIZE, fn_table, cookie, \
+	FPGA_VIRTEX2_OPS }
 
 #define XILINX_XC2V3000_DESC(iface, fn_table, cookie) \
-{ Xilinx_Virtex2, iface, XILINX_XC2V3000_SIZE, fn_table, cookie }
+{ xilinx_virtex2, iface, XILINX_XC2V3000_SIZE, fn_table, cookie, \
+	FPGA_VIRTEX2_OPS }
 
 #define XILINX_XC2V4000_DESC(iface, fn_table, cookie) \
-{ Xilinx_Virtex2, iface, XILINX_XC2V4000_SIZE, fn_table, cookie }
+{ xilinx_virtex2, iface, XILINX_XC2V4000_SIZE, fn_table, cookie, \
+	FPGA_VIRTEX2_OPS }
 
 #define XILINX_XC2V6000_DESC(iface, fn_table, cookie) \
-{ Xilinx_Virtex2, iface, XILINX_XC2V6000_SIZE, fn_table, cookie }
+{ xilinx_virtex2, iface, XILINX_XC2V6000_SIZE, fn_table, cookie, \
+	FPGA_VIRTEX2_OPS }
 
 #define XILINX_XC2V8000_DESC(iface, fn_table, cookie) \
-{ Xilinx_Virtex2, iface, XILINX_XC2V8000_SIZE, fn_table, cookie }
+{ xilinx_virtex2, iface, XILINX_XC2V8000_SIZE, fn_table, cookie, \
+	FPGA_VIRTEX2_OPS }
 
 #define XILINX_XC2V10000_DESC(iface, fn_table, cookie) \
-{ Xilinx_Virtex2, iface, XILINX_XC2V10000_SIZE, fn_table, cookie }
+{ xilinx_virtex2, iface, XILINX_XC2V10000_SIZE, fn_table, cookie, \
+	FPGA_VIRTEX2_OPS }
 
 #endif /* _VIRTEX2_H_ */