X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fzynqpl.h;h=5a34a17daefeb322861af3a16c967bad5fb9bd37;hb=af3106a12dd5d3a315f9f68b5fc0002c09f54d54;hp=1d37a51a04ef8e3f65f6cbddd166f7b27e227d55;hpb=4608f37918e5d93d6b2b6909b325a5e6fb0a2346;p=u-boot

diff --git a/include/zynqpl.h b/include/zynqpl.h
index 1d37a51a04..5a34a17dae 100644
--- a/include/zynqpl.h
+++ b/include/zynqpl.h
@@ -19,7 +19,10 @@ extern struct xilinx_fpga_op zynq_op;
 # define FPGA_ZYNQPL_OPS	NULL
 #endif
 
+#define XILINX_ZYNQ_7007S	0x3
 #define XILINX_ZYNQ_7010	0x2
+#define XILINX_ZYNQ_7012S	0x1c
+#define XILINX_ZYNQ_7014S	0x8
 #define XILINX_ZYNQ_7015	0x1b
 #define XILINX_ZYNQ_7020	0x7
 #define XILINX_ZYNQ_7030	0xc
@@ -28,7 +31,10 @@ extern struct xilinx_fpga_op zynq_op;
 #define XILINX_ZYNQ_7100	0x16
 
 /* Device Image Sizes */
+#define XILINX_XC7Z007S_SIZE	16669920/8
 #define XILINX_XC7Z010_SIZE	16669920/8
+#define XILINX_XC7Z012S_SIZE	28085344/8
+#define XILINX_XC7Z014S_SIZE	32364512/8
 #define XILINX_XC7Z015_SIZE	28085344/8
 #define XILINX_XC7Z020_SIZE	32364512/8
 #define XILINX_XC7Z030_SIZE	47839328/8
@@ -37,10 +43,22 @@ extern struct xilinx_fpga_op zynq_op;
 #define XILINX_XC7Z100_SIZE	139330784/8
 
 /* Descriptor Macros */
+#define XILINX_XC7Z007S_DESC(cookie) \
+{ xilinx_zynq, devcfg, XILINX_XC7Z007S_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
+	"7z007s" }
+
 #define XILINX_XC7Z010_DESC(cookie) \
 { xilinx_zynq, devcfg, XILINX_XC7Z010_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
 	"7z010" }
 
+#define XILINX_XC7Z012S_DESC(cookie) \
+{ xilinx_zynq, devcfg, XILINX_XC7Z012S_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
+	"7z012s" }
+
+#define XILINX_XC7Z014S_DESC(cookie) \
+{ xilinx_zynq, devcfg, XILINX_XC7Z014S_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
+	"7z014s" }
+
 #define XILINX_XC7Z015_DESC(cookie) \
 { xilinx_zynq, devcfg, XILINX_XC7Z015_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
 	"7z015" }