X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fzynqpl.h;h=9c63c016f504591dfd88c88a030b3d084844239d;hb=e8f80a5a58c9b506453cc0780687e8ed457d30a6;hp=1d37a51a04ef8e3f65f6cbddd166f7b27e227d55;hpb=ec0cc98f2cb7fa217ed0a1a54978e2d8f2fbc20c;p=u-boot

diff --git a/include/zynqpl.h b/include/zynqpl.h
index 1d37a51a04..9c63c016f5 100644
--- a/include/zynqpl.h
+++ b/include/zynqpl.h
@@ -1,10 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * (C) Copyright 2012-2013, Xilinx, Michal Simek
  *
  * (C) Copyright 2012
  * Joe Hershberger <joe.hershberger@ni.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #ifndef _ZYNQPL_H_
@@ -19,7 +18,10 @@ extern struct xilinx_fpga_op zynq_op;
 # define FPGA_ZYNQPL_OPS	NULL
 #endif
 
+#define XILINX_ZYNQ_7007S	0x3
 #define XILINX_ZYNQ_7010	0x2
+#define XILINX_ZYNQ_7012S	0x1c
+#define XILINX_ZYNQ_7014S	0x8
 #define XILINX_ZYNQ_7015	0x1b
 #define XILINX_ZYNQ_7020	0x7
 #define XILINX_ZYNQ_7030	0xc
@@ -28,7 +30,10 @@ extern struct xilinx_fpga_op zynq_op;
 #define XILINX_ZYNQ_7100	0x16
 
 /* Device Image Sizes */
+#define XILINX_XC7Z007S_SIZE	16669920/8
 #define XILINX_XC7Z010_SIZE	16669920/8
+#define XILINX_XC7Z012S_SIZE	28085344/8
+#define XILINX_XC7Z014S_SIZE	32364512/8
 #define XILINX_XC7Z015_SIZE	28085344/8
 #define XILINX_XC7Z020_SIZE	32364512/8
 #define XILINX_XC7Z030_SIZE	47839328/8
@@ -37,10 +42,22 @@ extern struct xilinx_fpga_op zynq_op;
 #define XILINX_XC7Z100_SIZE	139330784/8
 
 /* Descriptor Macros */
+#define XILINX_XC7Z007S_DESC(cookie) \
+{ xilinx_zynq, devcfg, XILINX_XC7Z007S_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
+	"7z007s" }
+
 #define XILINX_XC7Z010_DESC(cookie) \
 { xilinx_zynq, devcfg, XILINX_XC7Z010_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
 	"7z010" }
 
+#define XILINX_XC7Z012S_DESC(cookie) \
+{ xilinx_zynq, devcfg, XILINX_XC7Z012S_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
+	"7z012s" }
+
+#define XILINX_XC7Z014S_DESC(cookie) \
+{ xilinx_zynq, devcfg, XILINX_XC7Z014S_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
+	"7z014s" }
+
 #define XILINX_XC7Z015_DESC(cookie) \
 { xilinx_zynq, devcfg, XILINX_XC7Z015_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
 	"7z015" }