X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fzynqpl.h;h=cdfd8a205ab6c5dd5a0a6b4a1e504f4c3ce68472;hb=901af3e903c09c7681197a03367d82286f9f6e3f;hp=1d37a51a04ef8e3f65f6cbddd166f7b27e227d55;hpb=65afbbde6bd4429add8a644d8e2adbdbb812f7ec;p=u-boot

diff --git a/include/zynqpl.h b/include/zynqpl.h
index 1d37a51a04..cdfd8a205a 100644
--- a/include/zynqpl.h
+++ b/include/zynqpl.h
@@ -1,10 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * (C) Copyright 2012-2013, Xilinx, Michal Simek
  *
  * (C) Copyright 2012
  * Joe Hershberger <joe.hershberger@ni.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #ifndef _ZYNQPL_H_
@@ -12,23 +11,24 @@
 
 #include <xilinx.h>
 
-#if defined(CONFIG_FPGA_ZYNQPL)
 extern struct xilinx_fpga_op zynq_op;
-# define FPGA_ZYNQPL_OPS	&zynq_op
-#else
-# define FPGA_ZYNQPL_OPS	NULL
-#endif
 
-#define XILINX_ZYNQ_7010	0x2
-#define XILINX_ZYNQ_7015	0x1b
-#define XILINX_ZYNQ_7020	0x7
-#define XILINX_ZYNQ_7030	0xc
-#define XILINX_ZYNQ_7035	0x12
-#define XILINX_ZYNQ_7045	0x11
-#define XILINX_ZYNQ_7100	0x16
+#define XILINX_ZYNQ_XC7Z007S	0x3
+#define XILINX_ZYNQ_XC7Z010	0x2
+#define XILINX_ZYNQ_XC7Z012S	0x1c
+#define XILINX_ZYNQ_XC7Z014S	0x8
+#define XILINX_ZYNQ_XC7Z015	0x1b
+#define XILINX_ZYNQ_XC7Z020	0x7
+#define XILINX_ZYNQ_XC7Z030	0xc
+#define XILINX_ZYNQ_XC7Z035	0x12
+#define XILINX_ZYNQ_XC7Z045	0x11
+#define XILINX_ZYNQ_XC7Z100	0x16
 
 /* Device Image Sizes */
+#define XILINX_XC7Z007S_SIZE	16669920/8
 #define XILINX_XC7Z010_SIZE	16669920/8
+#define XILINX_XC7Z012S_SIZE	28085344/8
+#define XILINX_XC7Z014S_SIZE	32364512/8
 #define XILINX_XC7Z015_SIZE	28085344/8
 #define XILINX_XC7Z020_SIZE	32364512/8
 #define XILINX_XC7Z030_SIZE	47839328/8
@@ -36,33 +36,29 @@ extern struct xilinx_fpga_op zynq_op;
 #define XILINX_XC7Z045_SIZE	106571232/8
 #define XILINX_XC7Z100_SIZE	139330784/8
 
-/* Descriptor Macros */
-#define XILINX_XC7Z010_DESC(cookie) \
-{ xilinx_zynq, devcfg, XILINX_XC7Z010_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
-	"7z010" }
-
-#define XILINX_XC7Z015_DESC(cookie) \
-{ xilinx_zynq, devcfg, XILINX_XC7Z015_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
-	"7z015" }
-
-#define XILINX_XC7Z020_DESC(cookie) \
-{ xilinx_zynq, devcfg, XILINX_XC7Z020_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
-	"7z020" }
+/* Device Names */
+#define XILINX_XC7Z007S_NAME	"7z007s"
+#define XILINX_XC7Z010_NAME	"7z010"
+#define XILINX_XC7Z012S_NAME	"7z012s"
+#define XILINX_XC7Z014S_NAME	"7z014s"
+#define XILINX_XC7Z015_NAME	"7z015"
+#define XILINX_XC7Z020_NAME	"7z020"
+#define XILINX_XC7Z030_NAME	"7z030"
+#define XILINX_XC7Z035_NAME	"7z035"
+#define XILINX_XC7Z045_NAME	"7z045"
+#define XILINX_XC7Z100_NAME	"7z100"
 
-#define XILINX_XC7Z030_DESC(cookie) \
-{ xilinx_zynq, devcfg, XILINX_XC7Z030_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
-	"7z030" }
-
-#define XILINX_XC7Z035_DESC(cookie) \
-{ xilinx_zynq, devcfg, XILINX_XC7Z035_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
-	"7z035" }
-
-#define XILINX_XC7Z045_DESC(cookie) \
-{ xilinx_zynq, devcfg, XILINX_XC7Z045_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
-	"7z045" }
-
-#define XILINX_XC7Z100_DESC(cookie) \
-{ xilinx_zynq, devcfg, XILINX_XC7Z100_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
-	"7z100" }
+#if defined(CONFIG_FPGA)
+#define ZYNQ_DESC(name) { \
+	.idcode = XILINX_ZYNQ_XC##name, \
+	.fpga_size = XILINX_XC##name##_SIZE, \
+	.devicename = XILINX_XC##name##_NAME \
+	}
+#else
+#define ZYNQ_DESC(name) { \
+	.idcode = XILINX_ZYNQ_XC##name, \
+	.devicename = XILINX_XC##name##_NAME \
+	}
+#endif
 
 #endif /* _ZYNQPL_H_ */