X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=it87.c;h=e1d3b2ac603ff598e014db9fa86bd27bb734e656;hb=0e859b57439c8cbf123102d7d49c44258c050a92;hp=31c8ca959e3040d8c477d224fca48fd05514d1c7;hpb=57d4d8b8fae351e9d3b4965605055d917430e325;p=groeck-it87 diff --git a/it87.c b/it87.c index 31c8ca9..e1d3b2a 100644 --- a/it87.c +++ b/it87.c @@ -12,9 +12,11 @@ * * Supports: IT8603E Super I/O chip w/LPC interface * IT8607E Super I/O chip w/LPC interface + * IT8613E Super I/O chip w/LPC interface * IT8620E Super I/O chip w/LPC interface * IT8622E Super I/O chip w/LPC interface * IT8623E Super I/O chip w/LPC interface + * IT8625E Super I/O chip w/LPC interface * IT8628E Super I/O chip w/LPC interface * IT8655E Super I/O chip w/LPC interface * IT8665E Super I/O chip w/LPC interface @@ -75,24 +77,20 @@ #define DRVNAME "it87" -/* Necessary API not (yet) exported in upstream kernel */ -/* #define __IT87_USE_ACPI_MUTEX */ - enum chips { it87, it8712, it8716, it8718, it8720, it8721, it8728, it8732, it8771, it8772, it8781, it8782, it8783, it8786, it8790, - it8792, it8603, it8607, it8620, it8622, it8628, it8655, it8665, - it8686 }; + it8792, it8603, it8607, it8613, it8620, it8622, it8625, it8628, + it8655, it8665, it8686 }; static unsigned short force_id; module_param(force_id, ushort, 0); MODULE_PARM_DESC(force_id, "Override the detected device ID"); +static bool ignore_resource_conflict; +module_param(ignore_resource_conflict, bool, 0); +MODULE_PARM_DESC(ignore_resource_conflict, "Ignore ACPI resource conflict"); + static struct platform_device *it87_pdev[2]; -static bool it87_sio4e_broken; -#ifdef __IT87_USE_ACPI_MUTEX -static acpi_handle it87_acpi_sio_handle; -static char *it87_acpi_sio_mutex; -#endif #define REG_2E 0x2e /* The register to read/write */ #define REG_4E 0x4e /* Secondary register to read/write */ @@ -120,12 +118,6 @@ static inline int superio_inb(int ioreg, int reg) outb(reg, ioreg); val = inb(ioreg + 1); - if (it87_sio4e_broken && ioreg == 0x4e && val == 0xff) { - __superio_enter(ioreg); - outb(reg, ioreg); - val = inb(ioreg + 1); - pr_warn("Retry access 0x4e:0x%x -> 0x%x\n", reg, val); - } return val; } @@ -149,17 +141,6 @@ static inline void superio_select(int ioreg, int ldn) static inline int superio_enter(int ioreg) { -#ifdef __IT87_USE_ACPI_MUTEX - if (it87_acpi_sio_mutex) { - acpi_status status; - - status = acpi_acquire_mutex(NULL, it87_acpi_sio_mutex, 0x10); - if (ACPI_FAILURE(status)) { - pr_err("Failed to acquire ACPI mutex\n"); - return -EBUSY; - } - } -#endif /* * Try to reserve ioreg and ioreg + 1 for exclusive access. */ @@ -170,24 +151,16 @@ static inline int superio_enter(int ioreg) return 0; error: -#ifdef __IT87_USE_ACPI_MUTEX - if (it87_acpi_sio_mutex) - acpi_release_mutex(it87_acpi_sio_handle, NULL); -#endif return -EBUSY; } -static inline void superio_exit(int ioreg) +static inline void superio_exit(int ioreg, bool doexit) { - if (!it87_sio4e_broken || ioreg != 0x4e) { + if (doexit) { outb(0x02, ioreg); outb(0x02, ioreg + 1); } release_region(ioreg, 2); -#ifdef __IT87_USE_ACPI_MUTEX - if (it87_acpi_sio_mutex) - acpi_release_mutex(it87_acpi_sio_handle, NULL); -#endif } /* Logical device 4 registers */ @@ -210,9 +183,11 @@ static inline void superio_exit(int ioreg) #define IT8790E_DEVID 0x8790 #define IT8603E_DEVID 0x8603 #define IT8607E_DEVID 0x8607 +#define IT8613E_DEVID 0x8613 #define IT8620E_DEVID 0x8620 #define IT8622E_DEVID 0x8622 #define IT8623E_DEVID 0x8623 +#define IT8625E_DEVID 0x8625 #define IT8628E_DEVID 0x8628 #define IT8655E_DEVID 0x8655 #define IT8665E_DEVID 0x8665 @@ -297,9 +272,9 @@ static const u8 IT87_REG_FANX_8665[] = { 0x18, 0x19, 0x1a, 0x81, 0x83, 0x94 }; static const u8 IT87_REG_FANX_MIN_8665[] = { 0x1b, 0x1c, 0x1d, 0x85, 0x87, 0xb3 }; -static const u8 IT87_REG_TEMP_OFFSET[] = { 0x56, 0x57, 0x59, 0x5a, 0x91, 0x90 }; +static const u8 IT87_REG_TEMP_OFFSET[] = { 0x56, 0x57, 0x59, 0x5a, 0x90, 0x91 }; -static const u8 IT87_REG_TEMP_OFFSET_8686[] = { 0x56, 0x57, 0x59, 0x92, 0x91, 0x90 }; +static const u8 IT87_REG_TEMP_OFFSET_8686[] = { 0x56, 0x57, 0x59, 0x90, 0x91, 0x92 }; #define IT87_REG_FAN_MAIN_CTRL 0x13 #define IT87_REG_FAN_CTL 0x14 @@ -355,6 +330,8 @@ struct it87_devices { const char * const suffix; u32 features; u8 num_temp_limit; + u8 num_temp_offset; + u8 num_temp_map; /* Number of temperature sources for pwm */ u8 peci_mask; u8 old_peci_mask; }; @@ -363,7 +340,6 @@ struct it87_devices { #define FEAT_NEWER_AUTOPWM BIT(1) #define FEAT_OLD_AUTOPWM BIT(2) #define FEAT_16BIT_FANS BIT(3) -#define FEAT_TEMP_OFFSET BIT(4) #define FEAT_TEMP_PECI BIT(5) #define FEAT_TEMP_OLD_PECI BIT(6) #define FEAT_FAN16_CONFIG BIT(7) /* Need to enable 16-bit fans */ @@ -383,6 +359,8 @@ struct it87_devices { #define FEAT_BANK_SEL BIT(21) /* Chip has multi-bank support */ #define FEAT_SCALING BIT(22) /* Internal voltage scaling */ #define FEAT_FANCTL_ONOFF BIT(23) /* chip has FAN_CTL ON/OFF */ +#define FEAT_11MV_ADC BIT(24) +#define FEAT_NEW_TEMPMAP BIT(25) /* new temp input selection */ static const struct it87_devices it87_devices[] = { [it87] = { @@ -391,6 +369,8 @@ static const struct it87_devices it87_devices[] = { .features = FEAT_OLD_AUTOPWM | FEAT_FANCTL_ONOFF, /* may need to overwrite */ .num_temp_limit = 3, + .num_temp_offset = 0, + .num_temp_map = 3, }, [it8712] = { .name = "it8712", @@ -398,41 +378,51 @@ static const struct it87_devices it87_devices[] = { .features = FEAT_OLD_AUTOPWM | FEAT_VID | FEAT_FANCTL_ONOFF, /* may need to overwrite */ .num_temp_limit = 3, + .num_temp_offset = 0, + .num_temp_map = 3, }, [it8716] = { .name = "it8716", .suffix = "F", - .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID + .features = FEAT_16BIT_FANS | FEAT_VID | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF, .num_temp_limit = 3, + .num_temp_offset = 3, + .num_temp_map = 3, }, [it8718] = { .name = "it8718", .suffix = "F", - .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID + .features = FEAT_16BIT_FANS | FEAT_VID | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF, .num_temp_limit = 3, + .num_temp_offset = 3, + .num_temp_map = 3, .old_peci_mask = 0x4, }, [it8720] = { .name = "it8720", .suffix = "F", - .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID + .features = FEAT_16BIT_FANS | FEAT_VID | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF, .num_temp_limit = 3, + .num_temp_offset = 3, + .num_temp_map = 3, .old_peci_mask = 0x4, }, [it8721] = { .name = "it8721", .suffix = "F", .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS - | FEAT_TEMP_OFFSET | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI + | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_SCALING | FEAT_FANCTL_ONOFF, .num_temp_limit = 3, + .num_temp_offset = 3, + .num_temp_map = 3, .peci_mask = 0x05, .old_peci_mask = 0x02, /* Actually reports PCH */ }, @@ -440,20 +430,24 @@ static const struct it87_devices it87_devices[] = { .name = "it8728", .suffix = "F", .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS - | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_FIVE_FANS + | FEAT_TEMP_PECI | FEAT_FIVE_FANS | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_SCALING | FEAT_FANCTL_ONOFF, - .num_temp_limit = 3, + .num_temp_limit = 6, + .num_temp_offset = 3, + .num_temp_map = 3, .peci_mask = 0x07, }, [it8732] = { .name = "it8732", .suffix = "F", .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS - | FEAT_TEMP_OFFSET | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI + | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_FOUR_FANS | FEAT_FOUR_PWM | FEAT_FANCTL_ONOFF, .num_temp_limit = 3, + .num_temp_offset = 3, + .num_temp_map = 3, .peci_mask = 0x07, .old_peci_mask = 0x02, /* Actually reports PCH */ }, @@ -461,161 +455,213 @@ static const struct it87_devices it87_devices[] = { .name = "it8771", .suffix = "E", .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS - | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL + | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_SCALING | FEAT_FANCTL_ONOFF, /* PECI: guesswork */ /* 12mV ADC (OHM) */ /* 16 bit fans (OHM) */ /* three fans, always 16 bit (guesswork) */ .num_temp_limit = 3, + .num_temp_offset = 3, + .num_temp_map = 3, .peci_mask = 0x07, }, [it8772] = { .name = "it8772", .suffix = "E", .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS - | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL + | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_SCALING | FEAT_FANCTL_ONOFF, /* PECI (coreboot) */ /* 12mV ADC (HWSensors4, OHM) */ /* 16 bit fans (HWSensors4, OHM) */ /* three fans, always 16 bit (datasheet) */ .num_temp_limit = 3, + .num_temp_offset = 3, + .num_temp_map = 3, .peci_mask = 0x07, }, [it8781] = { .name = "it8781", .suffix = "F", - .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET + .features = FEAT_16BIT_FANS | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF, .num_temp_limit = 3, + .num_temp_offset = 3, + .num_temp_map = 3, .old_peci_mask = 0x4, }, [it8782] = { .name = "it8782", .suffix = "F", - .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET + .features = FEAT_16BIT_FANS | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF, .num_temp_limit = 3, + .num_temp_offset = 3, + .num_temp_map = 3, .old_peci_mask = 0x4, }, [it8783] = { .name = "it8783", .suffix = "E/F", - .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET + .features = FEAT_16BIT_FANS | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF, .num_temp_limit = 3, + .num_temp_offset = 3, + .num_temp_map = 3, .old_peci_mask = 0x4, }, [it8786] = { .name = "it8786", .suffix = "E", .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS - | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL + | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF, .num_temp_limit = 3, + .num_temp_offset = 3, + .num_temp_map = 3, .peci_mask = 0x07, }, [it8790] = { .name = "it8790", .suffix = "E", .features = FEAT_NEWER_AUTOPWM | FEAT_10_9MV_ADC | FEAT_SCALING - | FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI + | FEAT_16BIT_FANS | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF, .num_temp_limit = 3, + .num_temp_offset = 3, + .num_temp_map = 3, .peci_mask = 0x07, }, [it8792] = { .name = "it8792", .suffix = "E", .features = FEAT_NEWER_AUTOPWM | FEAT_10_9MV_ADC | FEAT_SCALING - | FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI + | FEAT_16BIT_FANS | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF, .num_temp_limit = 3, + .num_temp_offset = 3, + .num_temp_map = 3, .peci_mask = 0x07, }, [it8603] = { .name = "it8603", .suffix = "E", .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS - | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL + | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL | FEAT_AVCC3 | FEAT_PWM_FREQ2 | FEAT_SCALING, .num_temp_limit = 3, + .num_temp_offset = 3, + .num_temp_map = 4, .peci_mask = 0x07, }, [it8607] = { .name = "it8607", .suffix = "E", .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS - | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL + | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL | FEAT_NEW_TEMPMAP | FEAT_AVCC3 | FEAT_PWM_FREQ2 | FEAT_SCALING | FEAT_FANCTL_ONOFF, .num_temp_limit = 3, + .num_temp_offset = 3, + .num_temp_map = 6, + .peci_mask = 0x07, + }, + [it8613] = { + .name = "it8613", + .suffix = "E", + .features = FEAT_NEWER_AUTOPWM | FEAT_11MV_ADC | FEAT_16BIT_FANS + | FEAT_TEMP_PECI | FEAT_FIVE_FANS + | FEAT_FIVE_PWM | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 + | FEAT_AVCC3 | FEAT_SCALING | FEAT_NEW_TEMPMAP, + .num_temp_limit = 6, + .num_temp_offset = 6, + .num_temp_map = 6, .peci_mask = 0x07, }, [it8620] = { .name = "it8620", .suffix = "E", .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS - | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_SIX_FANS + | FEAT_TEMP_PECI | FEAT_SIX_FANS | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2 | FEAT_SIX_TEMP | FEAT_VIN3_5V | FEAT_SCALING | FEAT_FANCTL_ONOFF, .num_temp_limit = 3, + .num_temp_offset = 3, + .num_temp_map = 3, .peci_mask = 0x07, }, [it8622] = { .name = "it8622", .suffix = "E", .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS - | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_FIVE_FANS + | FEAT_TEMP_PECI | FEAT_FIVE_FANS | FEAT_FIVE_PWM | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_AVCC3 | FEAT_VIN3_5V | FEAT_SCALING, .num_temp_limit = 3, + .num_temp_offset = 3, + .num_temp_map = 4, .peci_mask = 0x07, }, + [it8625] = { + .name = "it8625", + .suffix = "E", + .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS + | FEAT_AVCC3 | FEAT_NEW_TEMPMAP + | FEAT_11MV_ADC | FEAT_IN7_INTERNAL | FEAT_SIX_FANS + | FEAT_SIX_PWM | FEAT_BANK_SEL | FEAT_SCALING, + .num_temp_limit = 6, + .num_temp_offset = 6, + .num_temp_map = 6, + }, [it8628] = { .name = "it8628", .suffix = "E", .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS - | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_SIX_FANS + | FEAT_TEMP_PECI | FEAT_SIX_FANS | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2 | FEAT_SIX_TEMP | FEAT_SCALING | FEAT_AVCC3 | FEAT_FANCTL_ONOFF, - .num_temp_limit = 3, + .num_temp_limit = 6, + .num_temp_offset = 3, + .num_temp_map = 3, .peci_mask = 0x07, }, [it8655] = { .name = "it8655", .suffix = "E", .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS - | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_AVCC3 + | FEAT_AVCC3 | FEAT_NEW_TEMPMAP | FEAT_SCALING | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_BANK_SEL, .num_temp_limit = 6, - .peci_mask = 0x07, + .num_temp_offset = 6, + .num_temp_map = 6, }, [it8665] = { .name = "it8665", .suffix = "E", .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS - | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_AVCC3 + | FEAT_AVCC3 | FEAT_NEW_TEMPMAP | FEAT_SCALING | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_SIX_FANS | FEAT_SIX_PWM | FEAT_BANK_SEL, .num_temp_limit = 6, - .peci_mask = 0x07, + .num_temp_offset = 6, + .num_temp_map = 6, }, [it8686] = { .name = "it8686", .suffix = "E", .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS - | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_SIX_FANS + | FEAT_SIX_FANS | FEAT_NEW_TEMPMAP | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2 | FEAT_SIX_TEMP | FEAT_BANK_SEL | FEAT_SCALING | FEAT_AVCC3, .num_temp_limit = 6, - .peci_mask = 0x07, + .num_temp_offset = 6, + .num_temp_map = 7, }, }; @@ -624,7 +670,6 @@ static const struct it87_devices it87_devices[] = { #define has_10_9mv_adc(data) ((data)->features & FEAT_10_9MV_ADC) #define has_newer_autopwm(data) ((data)->features & FEAT_NEWER_AUTOPWM) #define has_old_autopwm(data) ((data)->features & FEAT_OLD_AUTOPWM) -#define has_temp_offset(data) ((data)->features & FEAT_TEMP_OFFSET) #define has_temp_peci(data, nr) (((data)->features & FEAT_TEMP_PECI) && \ ((data)->peci_mask & BIT(nr))) #define has_temp_old_peci(data, nr) \ @@ -652,6 +697,8 @@ static const struct it87_devices it87_devices[] = { #define has_bank_sel(data) ((data)->features & FEAT_BANK_SEL) #define has_scaling(data) ((data)->features & FEAT_SCALING) #define has_fanctl_onoff(data) ((data)->features & FEAT_FANCTL_ONOFF) +#define has_11mv_adc(data) ((data)->features & FEAT_11MV_ADC) +#define has_new_tempmap(data) ((data)->features & FEAT_NEW_TEMPMAP) struct it87_sio_data { enum chips type; @@ -676,7 +723,6 @@ struct it87_data { const struct attribute_group *groups[7]; enum chips type; u32 features; - u8 bank; u8 peci_mask; u8 old_peci_mask; @@ -705,7 +751,8 @@ struct it87_data { u16 fan[NUM_FAN][2]; /* Register values, [nr][0]=fan, [1]=min */ u8 has_temp; /* Bitfield, temp sensors enabled */ s8 temp[NUM_TEMP][4]; /* [nr][0]=temp, [1]=min, [2]=max, [3]=offset */ - u8 num_temp_limit; /* Number of temp limit/offset registers */ + u8 num_temp_limit; /* Number of temperature limit registers */ + u8 num_temp_offset; /* Number of temperature offset registers */ u8 sensor; /* Register value (IT87_REG_TEMP_ENABLE) */ u8 extra; /* Register value (IT87_REG_TEMP_EXTRA) */ u8 fan_div[NUM_FAN_DIV];/* Register encoding, shifted right */ @@ -732,6 +779,9 @@ struct it87_data { u8 pwm_ctrl[NUM_PWM]; /* Register value */ u8 pwm_duty[NUM_PWM]; /* Manual PWM value set by user */ u8 pwm_temp_map[NUM_PWM];/* PWM to temp. chan. mapping (bits 1-0) */ + u8 pwm_temp_map_mask; /* 0x03 for old, 0x07 for new temp map */ + u8 pwm_temp_map_shift; /* 0 for old, 3 for new temp map */ + u8 pwm_num_temp_map; /* from config data, 3..7 depending on chip */ /* Automatic fan speed control registers */ u8 auto_pwm[NUM_AUTO_PWM][4]; /* [nr][3] is hard-coded */ @@ -746,6 +796,8 @@ static int adc_lsb(const struct it87_data *data, int nr) lsb = 120; else if (has_10_9mv_adc(data)) lsb = 109; + else if (has_11mv_adc(data)) + lsb = 110; else lsb = 160; if (data->in_scaled & BIT(nr)) @@ -816,6 +868,25 @@ static int DIV_TO_REG(int val) #define DIV_FROM_REG(val) BIT(val) +static u8 temp_map_from_reg(const struct it87_data *data, u8 reg) +{ + u8 map; + + map = (reg >> data->pwm_temp_map_shift) & data->pwm_temp_map_mask; + if (map >= data->pwm_num_temp_map) /* map is 0-based */ + map = 0; + + return map; +} + +static u8 temp_map_to_reg(const struct it87_data *data, int nr, u8 map) +{ + u8 ctrl = data->pwm_ctrl[nr]; + + return (ctrl & ~(data->pwm_temp_map_mask << data->pwm_temp_map_shift)) | + (map << data->pwm_temp_map_shift); +} + /* * PWM base frequencies. The frequency has to be divided by either 128 or 256, * depending on the chip type, to calculate the actual PWM frequency. @@ -849,16 +920,21 @@ static void _it87_write_value(struct it87_data *data, u8 reg, u8 value) outb_p(value, data->addr + IT87_DATA_REG_OFFSET); } -static void it87_set_bank(struct it87_data *data, u8 bank) +static u8 it87_set_bank(struct it87_data *data, u8 bank) { - if (has_bank_sel(data) && bank != data->bank) { + u8 _bank = bank; + + if (has_bank_sel(data)) { u8 breg = _it87_read_value(data, IT87_REG_BANK); - breg &= 0x1f; - breg |= (bank << 5); - data->bank = bank; - _it87_write_value(data, IT87_REG_BANK, breg); + _bank = breg >> 5; + if (bank != _bank) { + breg &= 0x1f; + breg |= (bank << 5); + _it87_write_value(data, IT87_REG_BANK, breg); + } } + return _bank; } /* @@ -868,8 +944,14 @@ static void it87_set_bank(struct it87_data *data, u8 bank) */ static int it87_read_value(struct it87_data *data, u16 reg) { - it87_set_bank(data, reg >> 8); - return _it87_read_value(data, reg & 0xff); + u8 bank; + int val; + + bank = it87_set_bank(data, reg >> 8); + val = _it87_read_value(data, reg & 0xff); + it87_set_bank(data, bank); + + return val; } /* @@ -879,22 +961,28 @@ static int it87_read_value(struct it87_data *data, u16 reg) */ static void it87_write_value(struct it87_data *data, u16 reg, u8 value) { - it87_set_bank(data, reg >> 8); + u8 bank; + + bank = it87_set_bank(data, reg >> 8); _it87_write_value(data, reg & 0xff, value); + it87_set_bank(data, bank); } static void it87_update_pwm_ctrl(struct it87_data *data, int nr) { - data->pwm_ctrl[nr] = it87_read_value(data, data->REG_PWM[nr]); + u8 ctrl; + + ctrl = it87_read_value(data, data->REG_PWM[nr]); + data->pwm_ctrl[nr] = ctrl; if (has_newer_autopwm(data)) { - data->pwm_temp_map[nr] = data->pwm_ctrl[nr] & 0x03; + data->pwm_temp_map[nr] = temp_map_from_reg(data, ctrl); data->pwm_duty[nr] = it87_read_value(data, IT87_REG_PWM_DUTY[nr]); } else { - if (data->pwm_ctrl[nr] & 0x80) /* Automatic mode */ - data->pwm_temp_map[nr] = data->pwm_ctrl[nr] & 0x03; + if (ctrl & 0x80) /* Automatic mode */ + data->pwm_temp_map[nr] = temp_map_from_reg(data, ctrl); else /* Manual mode */ - data->pwm_duty[nr] = data->pwm_ctrl[nr] & 0x7f; + data->pwm_duty[nr] = ctrl & 0x7f; } if (has_old_autopwm(data)) { @@ -993,7 +1081,7 @@ static struct it87_data *it87_update_device(struct device *dev) if (i >= data->num_temp_limit) continue; - if (has_temp_offset(data)) + if (i < data->num_temp_offset) data->temp[i][3] = it87_read_value(data, data->REG_TEMP_OFFSET[i]); @@ -1233,6 +1321,15 @@ static SENSOR_DEVICE_ATTR_2(temp6_max, S_IRUGO | S_IWUSR, show_temp, set_temp, static SENSOR_DEVICE_ATTR_2(temp6_offset, S_IRUGO | S_IWUSR, show_temp, set_temp, 5, 3); +static const u8 temp_types_8686[NUM_TEMP][9] = { + { 0, 8, 8, 8, 8, 8, 8, 8, 7 }, + { 0, 6, 8, 8, 6, 0, 0, 0, 7 }, + { 0, 6, 5, 8, 6, 0, 0, 0, 7 }, + { 4, 8, 8, 8, 8, 8, 8, 8, 7 }, + { 4, 6, 8, 8, 6, 0, 0, 0, 7 }, + { 4, 6, 5, 8, 6, 0, 0, 0, 7 }, +}; + static int get_temp_type(struct it87_data *data, int index) { u8 reg, extra; @@ -1243,34 +1340,22 @@ static int get_temp_type(struct it87_data *data, int index) u8 src1, src2; src1 = (it87_read_value(data, s1reg) >> ((index % 2) * 4)) & 0x0f; - src2 = it87_read_value(data, IT87_REG_TEMP_SRC2); switch (data->type) { case it8686: - switch (src1) { - case 0: - if (index >= 3) - return 4; - break; - case 1: - if (index == 1 || index == 2 || - index == 4 || index == 5) - return 6; - break; - case 2: - if (index == 2 || index == 6) - return 5; - break; - default: - break; - } + if (src1 < 9) + type = temp_types_8686[index][src1]; break; + case it8625: + if (index < 3) + break; case it8655: case it8665: if (src1 < 3) { index = src1; break; } + src2 = it87_read_value(data, IT87_REG_TEMP_SRC2); switch(src1) { case 3: type = (src2 & BIT(index)) ? 6 : 5; @@ -1289,8 +1374,8 @@ static int get_temp_type(struct it87_data *data, int index) return 0; } } - if (index >= 3) - return 0; + if (type || index >= 3) + return type; reg = it87_read_value(data, IT87_REG_TEMP_ENABLE); extra = it87_read_value(data, IT87_REG_TEMP_EXTRA); @@ -1598,6 +1683,7 @@ static ssize_t set_pwm_enable(struct device *dev, struct device_attribute *attr, } mutex_lock(&data->update_lock); + it87_update_pwm_ctrl(data, nr); if (val == 0) { if (nr < 3 && has_fanctl_onoff(data)) { @@ -1618,8 +1704,9 @@ static ssize_t set_pwm_enable(struct device *dev, struct device_attribute *attr, data->pwm_duty[nr]); /* and set manual mode */ if (has_newer_autopwm(data)) { - ctrl = (data->pwm_ctrl[nr] & 0x7c) | - data->pwm_temp_map[nr]; + ctrl = temp_map_to_reg(data, nr, + data->pwm_temp_map[nr]); + ctrl &= 0x7f; } else { ctrl = data->pwm_duty[nr]; } @@ -1630,9 +1717,11 @@ static ssize_t set_pwm_enable(struct device *dev, struct device_attribute *attr, u8 ctrl; if (has_newer_autopwm(data)) { - ctrl = (data->pwm_ctrl[nr] & 0x7c) | - data->pwm_temp_map[nr]; - if (val != 1) + ctrl = temp_map_to_reg(data, nr, + data->pwm_temp_map[nr]); + if (val == 1) + ctrl &= 0x7f; + else ctrl |= 0x80; } else { ctrl = (val == 1 ? data->pwm_duty[nr] : 0x80); @@ -1735,15 +1824,8 @@ static ssize_t show_pwm_temp_map(struct device *dev, struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); struct it87_data *data = it87_update_device(dev); int nr = sensor_attr->index; - int map; - map = data->pwm_temp_map[nr]; - if (map >= 3) - map = 0; /* Should never happen */ - if (nr >= 3) /* pwm channels 3..6 map to temp4..6 */ - map += 3; - - return sprintf(buf, "%d\n", (int)BIT(map)); + return sprintf(buf, "%d\n", data->pwm_temp_map[nr] + 1); } static ssize_t set_pwm_temp_map(struct device *dev, @@ -1753,39 +1835,26 @@ static ssize_t set_pwm_temp_map(struct device *dev, struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); struct it87_data *data = dev_get_drvdata(dev); int nr = sensor_attr->index; - long val; - u8 reg; + unsigned long val; + u8 map; - if (kstrtol(buf, 10, &val) < 0) + if (kstrtoul(buf, 10, &val) < 0) return -EINVAL; - if (nr >= 3) - val -= 3; - - switch (val) { - case BIT(0): - reg = 0x00; - break; - case BIT(1): - reg = 0x01; - break; - case BIT(2): - reg = 0x02; - break; - default: + if (!val || val > data->pwm_num_temp_map) return -EINVAL; - } + + map = val - 1; mutex_lock(&data->update_lock); it87_update_pwm_ctrl(data, nr); - data->pwm_temp_map[nr] = reg; + data->pwm_temp_map[nr] = map; /* * If we are in automatic mode, write the temp mapping immediately; * otherwise, just store it for later use. */ if (data->pwm_ctrl[nr] & 0x80) { - data->pwm_ctrl[nr] = (data->pwm_ctrl[nr] & 0xfc) | - data->pwm_temp_map[nr]; + data->pwm_ctrl[nr] = temp_map_to_reg(data, nr, map); it87_write_value(data, data->REG_PWM[nr], data->pwm_ctrl[nr]); } mutex_unlock(&data->update_lock); @@ -2259,7 +2328,8 @@ static ssize_t show_label(struct device *dev, struct device_attribute *attr, if (has_vin3_5v(data) && nr == 0) label = labels[0]; - else if (has_12mv_adc(data) || has_10_9mv_adc(data)) + else if (has_12mv_adc(data) || has_10_9mv_adc(data) || + has_11mv_adc(data)) label = labels_it8721[nr]; else label = labels[nr]; @@ -2380,7 +2450,7 @@ static umode_t it87_temp_is_visible(struct kobject *kobj, return attr->mode; } - if (a == 5 && !has_temp_offset(data)) + if (a == 5 && i >= data->num_temp_offset) return 0; if (a == 6 && !data->has_beep) @@ -2709,9 +2779,10 @@ static const struct attribute_group it87_group_auto_pwm = { static int __init it87_find(int sioaddr, unsigned short *address, struct it87_sio_data *sio_data) { - int err; - u16 chip_type; const struct it87_devices *config; + bool doexit = true; + u16 chip_type; + int err; err = superio_enter(sioaddr); if (err) @@ -2753,6 +2824,13 @@ static int __init it87_find(int sioaddr, unsigned short *address, break; case IT8792E_DEVID: sio_data->type = it8792; + /* + * Disabling configuration mode on IT8792E can result in system + * hang-ups and access failures to the Super-IO chip at the + * second SIO address. Never exit configuration mode on this + * chip to avoid the problem. + */ + doexit = false; break; case IT8771E_DEVID: sio_data->type = it8771; @@ -2774,6 +2852,7 @@ static int __init it87_find(int sioaddr, unsigned short *address, break; case IT8790E_DEVID: sio_data->type = it8790; + doexit = false; /* See IT8792E comment above */ break; case IT8603E_DEVID: case IT8623E_DEVID: @@ -2782,12 +2861,18 @@ static int __init it87_find(int sioaddr, unsigned short *address, case IT8607E_DEVID: sio_data->type = it8607; break; + case IT8613E_DEVID: + sio_data->type = it8613; + break; case IT8620E_DEVID: sio_data->type = it8620; break; case IT8622E_DEVID: sio_data->type = it8622; break; + case IT8625E_DEVID: + sio_data->type = it8625; + break; case IT8628E_DEVID: sio_data->type = it8628; break; @@ -2943,11 +3028,55 @@ static int __init it87_find(int sioaddr, unsigned short *address, if (reg29 & BIT(2)) sio_data->skip_fan |= BIT(1); - if (sio_data->type == it8603) { + switch (sio_data->type) { + case it8603: sio_data->skip_in |= BIT(5); /* No VIN5 */ sio_data->skip_in |= BIT(6); /* No VIN6 */ + break; + case it8607: + sio_data->skip_pwm |= BIT(0);/* No fan1 */ + sio_data->skip_fan |= BIT(0); + default: + break; + } + + sio_data->beep_pin = superio_inb(sioaddr, + IT87_SIO_BEEP_PIN_REG) & 0x3f; + } else if (sio_data->type == it8613) { + int reg27, reg29, reg2a; + + superio_select(sioaddr, GPIO); + + /* Check for pwm3, fan3, pwm5, fan5 */ + reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG); + if (reg27 & BIT(1)) + sio_data->skip_fan |= BIT(4); + if (reg27 & BIT(3)) + sio_data->skip_pwm |= BIT(4); + if (reg27 & BIT(6)) + sio_data->skip_pwm |= BIT(2); + if (reg27 & BIT(7)) + sio_data->skip_fan |= BIT(2); + + /* Check for pwm2, fan2 */ + reg29 = superio_inb(sioaddr, IT87_SIO_GPIO5_REG); + if (reg29 & BIT(1)) + sio_data->skip_pwm |= BIT(1); + if (reg29 & BIT(2)) + sio_data->skip_fan |= BIT(1); + + /* Check for pwm4, fan4 */ + reg2a = superio_inb(sioaddr, IT87_SIO_PINX1_REG); + if (!(reg2a & BIT(0)) || (reg29 & BIT(7))) { + sio_data->skip_fan |= BIT(3); + sio_data->skip_pwm |= BIT(3); } + sio_data->skip_pwm |= BIT(0); /* No pwm1 */ + sio_data->skip_fan |= BIT(0); /* No fan1 */ + sio_data->skip_in |= BIT(3); /* No VIN3 */ + sio_data->skip_in |= BIT(6); /* No VIN6 */ + sio_data->beep_pin = superio_inb(sioaddr, IT87_SIO_BEEP_PIN_REG) & 0x3f; } else if (sio_data->type == it8620 || sio_data->type == it8628 || @@ -3094,44 +3223,57 @@ static int __init it87_find(int sioaddr, unsigned short *address, sio_data->beep_pin = superio_inb(sioaddr, IT87_SIO_BEEP_PIN_REG) & 0x3f; - } else if (sio_data->type == it8665) { - int reg; + } else if (sio_data->type == it8665 || sio_data->type == it8625) { + int reg27, reg29, reg2d, regd3; superio_select(sioaddr, GPIO); - /* Check for pwm2 */ - reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG); - if (reg & BIT(1)) - sio_data->skip_pwm |= BIT(1); + reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG); + reg29 = superio_inb(sioaddr, IT87_SIO_GPIO5_REG); + reg2d = superio_inb(sioaddr, IT87_SIO_PINX4_REG); + regd3 = superio_inb(sioaddr, IT87_SIO_GPIO9_REG); - /* Check for fan2 */ - reg = superio_inb(sioaddr, IT87_SIO_PINX4_REG); - if (reg & BIT(4)) + /* Check for pwm2, fan2 */ + if (reg29 & BIT(1)) + sio_data->skip_pwm |= BIT(1); + if (reg2d & BIT(4)) sio_data->skip_fan |= BIT(1); /* Check for pwm3, fan3 */ - reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG); - if (reg & BIT(6)) + if (reg27 & BIT(6)) sio_data->skip_pwm |= BIT(2); - if (reg & BIT(7)) + if (reg27 & BIT(7)) sio_data->skip_fan |= BIT(2); - /* Check for pwm5, fan5 */ - reg = superio_inb(sioaddr, IT87_SIO_GPIO2_REG); - if (reg & BIT(5)) - sio_data->skip_pwm |= BIT(4); - if (!(reg & BIT(4))) - sio_data->skip_fan |= BIT(4); + /* Check for pwm4, fan4, pwm5, fan5 */ + if (sio_data->type == it8625) { + int reg25 = superio_inb(sioaddr, IT87_SIO_GPIO1_REG); + + if (reg25 & BIT(6)) + sio_data->skip_fan |= BIT(3); + if (reg25 & BIT(5)) + sio_data->skip_pwm |= BIT(3); + if (reg27 & BIT(3)) + sio_data->skip_pwm |= BIT(4); + if (reg27 & BIT(1)) + sio_data->skip_fan |= BIT(4); + } else { + int reg26 = superio_inb(sioaddr, IT87_SIO_GPIO2_REG); + + if (regd3 & BIT(2)) + sio_data->skip_pwm |= BIT(3); + if (regd3 & BIT(3)) + sio_data->skip_fan |= BIT(3); + if (reg26 & BIT(5)) + sio_data->skip_pwm |= BIT(4); + if (!(reg26 & BIT(4))) + sio_data->skip_fan |= BIT(4); + } - /* Check for pwm4, fan4, pwm6, fan6 */ - reg = superio_inb(sioaddr, IT87_SIO_GPIO9_REG); - if (reg & BIT(2)) - sio_data->skip_pwm |= BIT(3); - if (reg & BIT(3)) - sio_data->skip_fan |= BIT(3); - if (reg & BIT(0)) + /* Check for pwm6, fan6 */ + if (regd3 & BIT(0)) sio_data->skip_pwm |= BIT(5); - if (reg & BIT(1)) + if (regd3 & BIT(1)) sio_data->skip_fan |= BIT(5); sio_data->beep_pin = superio_inb(sioaddr, @@ -3241,20 +3383,17 @@ static int __init it87_find(int sioaddr, unsigned short *address, pr_info("Beeping is supported\n"); exit: - superio_exit(sioaddr); + superio_exit(sioaddr, doexit); return err; } -/* Called when we have found a new IT87. */ -static void it87_init_device(struct platform_device *pdev) +static void it87_init_regs(struct platform_device *pdev) { - struct it87_sio_data *sio_data = dev_get_platdata(&pdev->dev); struct it87_data *data = platform_get_drvdata(pdev); - int tmp, i; - u8 mask; /* Initialize chip specific register pointers */ switch (data->type) { + case it8628: case it8686: data->REG_FAN = IT87_REG_FAN; data->REG_FANX = IT87_REG_FANX; @@ -3265,6 +3404,7 @@ static void it87_init_device(struct platform_device *pdev) data->REG_TEMP_LOW = IT87_REG_TEMP_LOW_8686; data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH_8686; break; + case it8625: case it8655: case it8665: data->REG_FAN = IT87_REG_FAN_8665; @@ -3286,6 +3426,16 @@ static void it87_init_device(struct platform_device *pdev) data->REG_TEMP_LOW = IT87_REG_TEMP_LOW; data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH; break; + case it8613: + data->REG_FAN = IT87_REG_FAN; + data->REG_FANX = IT87_REG_FANX; + data->REG_FAN_MIN = IT87_REG_FAN_MIN; + data->REG_FANX_MIN = IT87_REG_FANX_MIN; + data->REG_PWM = IT87_REG_PWM_8665; + data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET; + data->REG_TEMP_LOW = IT87_REG_TEMP_LOW; + data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH; + break; default: data->REG_FAN = IT87_REG_FAN; data->REG_FANX = IT87_REG_FANX; @@ -3297,6 +3447,23 @@ static void it87_init_device(struct platform_device *pdev) data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH; break; } +} + +/* Called when we have found a new IT87. */ +static void it87_init_device(struct platform_device *pdev) +{ + struct it87_sio_data *sio_data = dev_get_platdata(&pdev->dev); + struct it87_data *data = platform_get_drvdata(pdev); + int tmp, i; + u8 mask; + + if (has_new_tempmap(data)) { + data->pwm_temp_map_shift = 3; + data->pwm_temp_map_mask = 0x07; + } else { + data->pwm_temp_map_shift = 0; + data->pwm_temp_map_mask = 0x03; + } /* * For each PWM channel: @@ -3304,7 +3471,7 @@ static void it87_init_device(struct platform_device *pdev) * the fan to full speed by default. * - If it is in manual mode, we need a mapping to temperature * channels to use when later setting to automatic mode later. - * Use a 1:1 mapping by default (we are clueless.) + * Map to the first sensor by default (we are clueless.) * In both cases, the value can (and should) be changed by the user * prior to switching to a different mode. * Note that this is no longer needed for the IT8721F and later, as @@ -3312,7 +3479,7 @@ static void it87_init_device(struct platform_device *pdev) * manual duty cycle. */ for (i = 0; i < NUM_AUTO_PWM; i++) { - data->pwm_temp_map[i] = i; + data->pwm_temp_map[i] = 0; data->pwm_duty[i] = 0x7f; /* Full speed */ data->auto_pwm[i][3] = 0x7f; /* Full speed, hard-coded */ } @@ -3385,6 +3552,7 @@ static void it87_init_device(struct platform_device *pdev) if (tmp & BIT(2)) data->has_fan |= BIT(5); /* fan6 enabled */ break; + case it8625: case it8665: tmp = it87_read_value(data, IT87_REG_FAN_DIV); if (tmp & BIT(3)) @@ -3502,9 +3670,10 @@ static int it87_probe(struct platform_device *pdev) data->type = sio_data->type; data->features = it87_devices[sio_data->type].features; data->num_temp_limit = it87_devices[sio_data->type].num_temp_limit; + data->num_temp_offset = it87_devices[sio_data->type].num_temp_offset; + data->pwm_num_temp_map = it87_devices[sio_data->type].num_temp_map; data->peci_mask = it87_devices[sio_data->type].peci_mask; data->old_peci_mask = it87_devices[sio_data->type].old_peci_mask; - data->bank = 0xff; /* * IT8705F Datasheet 0.4.1, 3h == Version G. @@ -3538,6 +3707,9 @@ static int it87_probe(struct platform_device *pdev) mutex_init(&data->update_lock); + /* Initialize register pointers */ + it87_init_regs(pdev); + /* Check PWM configuration */ enable_pwm_interface = it87_check_pwm(dev); @@ -3642,8 +3814,10 @@ static int __init it87_device_add(int index, unsigned short address, int err; err = acpi_check_resource_conflict(&res); - if (err) - return err; + if (err) { + if (!ignore_resource_conflict) + return err; + } pdev = platform_device_alloc(DRVNAME, address); if (!pdev) @@ -3677,19 +3851,26 @@ exit_device_put: } struct it87_dmi_data { - bool sio4e_broken; /* SIO accesses @ 0x4e are broken */ - char *sio_mutex; /* SIO ACPI mutex */ + bool sio2_force_config; /* force sio2 into configuration mode */ u8 skip_pwm; /* pwm channels to skip for this board */ }; /* - * On Gigabyte AB350 boards, accesses to the Super-IO chip - * at address 0x4e/0x4f can result in a system hang. - * Accesses to address 0x2e/0x2f need to be mutex protected. + * On various Gigabyte AM4 boards (AB350, AX370), the second Super-IO chip + * (IT8792E) needs to be in configuration mode before accessing the first + * due to a bug in IT8792E which otherwise results in LPC bus access errors. + * This needs to be done before accessing the first Super-IO chip since + * the second chip may have been accessed prior to loading this driver. + * + * The problem is also reported to affect IT8795E, which is used on X299 boards + * and has the same chip ID as IT8792E (0x8733). It also appears to affect + * systems with IT8790E, which is used on some Z97X-Gaming boards as well as + * Z87X-OC. + * DMI entries for those systems will be added as they become available and + * as the problem is confirmed to affect those boards. */ -static struct it87_dmi_data gigabyte_ab350_gaming = { - .sio4e_broken = true, - .sio_mutex = "\\_SB.PCI0.SBRG.SIO1.MUT0", +static struct it87_dmi_data gigabyte_sio2_force = { + .sio2_force_config = true, }; /* @@ -3708,16 +3889,23 @@ static const struct dmi_system_id it87_dmi_table[] __initconst = { { .matches = { DMI_MATCH(DMI_SYS_VENDOR, "Gigabyte Technology Co., Ltd."), - DMI_MATCH(DMI_BOARD_NAME, "AB350-Gaming-CF"), + DMI_MATCH(DMI_BOARD_NAME, "AB350"), }, - .driver_data = &gigabyte_ab350_gaming, + .driver_data = &gigabyte_sio2_force, }, { .matches = { DMI_MATCH(DMI_SYS_VENDOR, "Gigabyte Technology Co., Ltd."), - DMI_MATCH(DMI_BOARD_NAME, "AB350-Gaming 3-CF"), + DMI_MATCH(DMI_BOARD_NAME, "AX370"), }, - .driver_data = &gigabyte_ab350_gaming, + .driver_data = &gigabyte_sio2_force, + }, + { + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "Gigabyte Technology Co., Ltd."), + DMI_MATCH(DMI_BOARD_NAME, "Z97X-Gaming G1"), + }, + .driver_data = &gigabyte_sio2_force, }, { .matches = { @@ -3742,30 +3930,13 @@ static int __init sm_it87_init(void) if (dmi) dmi_data = dmi->driver_data; - if (dmi_data) { - it87_sio4e_broken = dmi_data->sio4e_broken; -#ifdef __IT87_USE_ACPI_MUTEX - if (dmi_data->sio_mutex) { - static acpi_status status; - - status = acpi_get_handle(NULL, dmi_data->sio_mutex, - &it87_acpi_sio_handle); - if (ACPI_SUCCESS(status)) { - it87_acpi_sio_mutex = dmi_data->sio_mutex; - pr_debug("Found ACPI SIO mutex %s\n", - dmi_data->sio_mutex); - } else { - pr_warn("ACPI SIO mutex %s not found\n", - dmi_data->sio_mutex); - } - } -#endif /* __IT87_USE_ACPI_MUTEX */ - } - err = platform_driver_register(&it87_driver); if (err) return err; + if (dmi_data && dmi_data->sio2_force_config) + __superio_enter(REG_4E); + for (i = 0; i < ARRAY_SIZE(sioaddr); i++) { memset(&sio_data, 0, sizeof(struct it87_sio_data)); isa_address = 0;