X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=lib_ppc%2Fcache.c;h=338b08bd77005f0b477ad594ce1c37d588943bf2;hb=cd1011db80287eef933d1599b74cff1116c93134;hp=bec092e4cebc64ff6d90ae6bbe2df3f8c044dee1;hpb=affae2bff825c1a8d2cfeaf7b270188d251d39d2;p=u-boot

diff --git a/lib_ppc/cache.c b/lib_ppc/cache.c
index bec092e4ce..338b08bd77 100644
--- a/lib_ppc/cache.c
+++ b/lib_ppc/cache.c
@@ -22,26 +22,32 @@
  */
 
 #include <common.h>
+#include <asm/cache.h>
+#include <watchdog.h>
 
-void flush_cache (ulong start_addr, ulong size)
+void flush_cache(ulong start_addr, ulong size)
 {
-	ulong addr, end_addr = start_addr + size;
+#ifndef CONFIG_5xx
+	ulong addr, start, end;
 
-	if (CFG_CACHELINE_SIZE) {
-		addr = start_addr & (CFG_CACHELINE_SIZE - 1);
-		for (addr = start_addr;
-		     addr < end_addr;
-		     addr += CFG_CACHELINE_SIZE) {
-			asm ("dcbst 0,%0": :"r" (addr));
-		}
-		asm ("sync");	/* Wait for all dcbst to complete on bus */
+	start = start_addr & ~(CONFIG_SYS_CACHELINE_SIZE - 1);
+	end = start_addr + size - 1;
 
-		for (addr = start_addr;
-		     addr < end_addr;
-		     addr += CFG_CACHELINE_SIZE) {
-			asm ("icbi 0,%0": :"r" (addr));
-		}
+	for (addr = start; (addr <= end) && (addr >= start);
+			addr += CONFIG_SYS_CACHELINE_SIZE) {
+		asm volatile("dcbst 0,%0" : : "r" (addr) : "memory");
+		WATCHDOG_RESET();
 	}
-	asm ("sync");		/* Always flush prefetch queue in any case */
-	asm ("isync");
+	/* wait for all dcbst to complete on bus */
+	asm volatile("sync" : : : "memory");
+
+	for (addr = start; (addr <= end) && (addr >= start);
+			addr += CONFIG_SYS_CACHELINE_SIZE) {
+		asm volatile("icbi 0,%0" : : "r" (addr) : "memory");
+		WATCHDOG_RESET();
+	}
+	asm volatile("sync" : : : "memory");
+	/* flush prefetch queue */
+	asm volatile("isync" : : : "memory");
+#endif
 }