X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=nand_spl%2Fnand_boot.c;h=563a80b9537705e88019c582c0fdb4e2072490e1;hb=b2b15ebb66f0e7958dff8916077da0aceb2982a8;hp=840a59659674f442829c2038770b6293e559ea4a;hpb=d1246a4bb1ae9502ff540291423f1bb02d1e808c;p=u-boot

diff --git a/nand_spl/nand_boot.c b/nand_spl/nand_boot.c
index 840a596596..563a80b953 100644
--- a/nand_spl/nand_boot.c
+++ b/nand_spl/nand_boot.c
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2006-2007
+ * (C) Copyright 2006-2008
  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  *
  * This program is free software; you can redistribute it and/or
@@ -28,6 +28,10 @@ static int nand_ecc_pos[] = CFG_NAND_ECCPOS;
 
 extern void board_nand_init(struct nand_chip *nand);
 
+#if (CFG_NAND_PAGE_SIZE <= 512)
+/*
+ * NAND command for small page NAND devices (512)
+ */
 static int nand_command(struct mtd_info *mtd, int block, int page, int offs, u8 cmd)
 {
 	struct nand_chip *this = mtd->priv;
@@ -65,6 +69,64 @@ static int nand_command(struct mtd_info *mtd, int block, int page, int offs, u8
 
 	return 0;
 }
+#else
+/*
+ * NAND command for large page NAND devices (2k)
+ */
+static int nand_command(struct mtd_info *mtd, int block, int page, int offs, u8 cmd)
+{
+	struct nand_chip *this = mtd->priv;
+	int page_offs = offs;
+	int page_addr = page + block * CFG_NAND_PAGE_COUNT;
+
+	if (this->dev_ready)
+		this->dev_ready(mtd);
+	else
+		CFG_NAND_READ_DELAY;
+
+	/* Emulate NAND_CMD_READOOB */
+	if (cmd == NAND_CMD_READOOB) {
+		page_offs += CFG_NAND_PAGE_SIZE;
+		cmd = NAND_CMD_READ0;
+	}
+
+	/* Begin command latch cycle */
+	this->hwcontrol(mtd, NAND_CTL_SETCLE);
+	this->write_byte(mtd, cmd);
+	/* Set ALE and clear CLE to start address cycle */
+	this->hwcontrol(mtd, NAND_CTL_CLRCLE);
+	this->hwcontrol(mtd, NAND_CTL_SETALE);
+	/* Column address */
+	this->write_byte(mtd, page_offs & 0xff);			/* A[7:0] */
+	this->write_byte(mtd, (uchar)((page_offs >> 8) & 0xff));	/* A[11:9] */
+	/* Row address */
+	this->write_byte(mtd, (uchar)(page_addr & 0xff));		/* A[19:12] */
+	this->write_byte(mtd, (uchar)((page_addr >> 8) & 0xff));	/* A[27:20] */
+#ifdef CFG_NAND_5_ADDR_CYCLE
+	/* One more address cycle for devices > 128MiB */
+	this->write_byte(mtd, (uchar)((page_addr >> 16) & 0x0f));	/* A[xx:28] */
+#endif
+	/* Latch in address */
+	this->hwcontrol(mtd, NAND_CTL_CLRALE);
+
+	/* Begin command latch cycle */
+	this->hwcontrol(mtd, NAND_CTL_SETCLE);
+	/* Write out the start read command */
+	this->write_byte(mtd, NAND_CMD_READSTART);
+	/* End command latch cycle */
+	this->hwcontrol(mtd, NAND_CTL_CLRCLE);
+
+	/*
+	 * Wait a while for the data to be ready
+	 */
+	if (this->dev_ready)
+		this->dev_ready(mtd);
+	else
+		CFG_NAND_READ_DELAY;
+
+	return 0;
+}
+#endif
 
 static int nand_is_bad_block(struct mtd_info *mtd, int block)
 {
@@ -73,7 +135,7 @@ static int nand_is_bad_block(struct mtd_info *mtd, int block)
 	nand_command(mtd, block, 0, CFG_NAND_BAD_BLOCK_POS, NAND_CMD_READOOB);
 
 	/*
-	 * Read on byte
+	 * Read one byte
 	 */
 	if (this->read_byte(mtd) != 0xff)
 		return 1;
@@ -159,19 +221,18 @@ static int nand_load(struct mtd_info *mtd, int offs, int uboot_size, uchar *dst)
 	return 0;
 }
 
+/*
+ * The main entry for NAND booting. It's necessary that SDRAM is already
+ * configured and available since this code loads the main U-Boot image
+ * from NAND into SDRAM and starts it from there.
+ */
 void nand_boot(void)
 {
-	ulong mem_size;
 	struct nand_chip nand_chip;
 	nand_info_t nand_info;
 	int ret;
 	void (*uboot)(void);
 
-	/*
-	 * Init sdram, so we have access to memory
-	 */
-	mem_size = initdram(0);
-
 	/*
 	 * Init board specific nand support
 	 */