X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=nand_spl%2Fnand_boot_fsl_elbc.c;h=9547d44238885fbd36e23eda1403f5c79f5d6b79;hb=aa44a45f734d06e3536e1a7461733b52aca4869c;hp=0d2378ee894d29d084fe19ab7bcd1c684ff28834;hpb=8641ff266ae6638da201747c239fd39ba34c4958;p=u-boot

diff --git a/nand_spl/nand_boot_fsl_elbc.c b/nand_spl/nand_boot_fsl_elbc.c
index 0d2378ee89..9547d44238 100644
--- a/nand_spl/nand_boot_fsl_elbc.c
+++ b/nand_spl/nand_boot_fsl_elbc.c
@@ -25,7 +25,6 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <asm/immap_83xx.h>
 #include <asm/fsl_lbc.h>
 #include <linux/mtd/nand.h>
 
@@ -33,7 +32,7 @@
 
 static void nand_wait(void)
 {
-	lbus83xx_t *regs = (lbus83xx_t *)(CFG_IMMR + 0x5000);
+	fsl_lbc_t *regs = LBC_BASE_ADDR;
 
 	for (;;) {
 		uint32_t status = in_be32(&regs->ltesr);
@@ -50,8 +49,8 @@ static void nand_wait(void)
 
 static void nand_load(unsigned int offs, int uboot_size, uchar *dst)
 {
-	lbus83xx_t *regs = (lbus83xx_t *)(CFG_IMMR + 0x5000);
-	uchar *buf = (uchar *)CFG_NAND_BASE;
+	fsl_lbc_t *regs = LBC_BASE_ADDR;
+	uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE;
 	int large = in_be32(&regs->bank[0].or) & OR_FCM_PGS;
 	int block_shift = large ? 17 : 14;
 	int block_size = 1 << block_shift;
@@ -120,7 +119,7 @@ static void nand_load(unsigned int offs, int uboot_size, uchar *dst)
 
 			pos += page_size;
 			offs += page_size;
-		} while (offs & (block_size - 1));
+		} while ((offs & (block_size - 1)) && (pos < uboot_size));
 	}
 }
 
@@ -133,18 +132,21 @@ void nand_boot(void)
 {
 	__attribute__((noreturn)) void (*uboot)(void);
 
-	udelay(1000000);
-
 	/*
 	 * Load U-Boot image from NAND into RAM
 	 */
-	nand_load(CFG_NAND_U_BOOT_OFFS, CFG_NAND_U_BOOT_SIZE,
-	          (uchar *)CFG_NAND_U_BOOT_DST);
+	nand_load(CONFIG_SYS_NAND_U_BOOT_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE,
+	          (uchar *)CONFIG_SYS_NAND_U_BOOT_DST);
 
 	/*
 	 * Jump to U-Boot image
 	 */
 	puts("transfering control\n");
-	uboot = (void *)CFG_NAND_U_BOOT_START;
+	/*
+	 * Clean d-cache and invalidate i-cache, to
+	 * make sure that no stale data is executed.
+	 */
+	flush_cache(CONFIG_SYS_NAND_U_BOOT_DST, CONFIG_SYS_NAND_U_BOOT_SIZE);
+	uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
 	uboot();
 }