X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=nct6775.c;h=321308538c04f3ff4c5f3b3e424645cd3565256c;hb=6b4fdc1510363003aa228976270fb1916591aede;hp=f32346d36bf62f09578a8056dc5fc89a8b8b8c73;hpb=2e3aa9314eb94b4762134c281d3c6d70e4a7a21c;p=groeck-nct6775 diff --git a/nct6775.c b/nct6775.c index f32346d..3213085 100644 --- a/nct6775.c +++ b/nct6775.c @@ -117,11 +117,19 @@ superio_select(int ioreg, int ld) outb(ld, ioreg + 1); } -static inline void +static inline int superio_enter(int ioreg) { + /* + * Try to reserve and for exclusive access. + */ + if (!request_muxed_region(ioreg, 2, DRVNAME)) + return -EBUSY; + outb(0x87, ioreg); outb(0x87, ioreg); + + return 0; } static inline void @@ -130,6 +138,7 @@ superio_exit(int ioreg) outb(0xaa, ioreg); outb(0x02, ioreg); outb(0x02, ioreg + 1); + release_region(ioreg, 2); } /* @@ -241,6 +250,8 @@ static const u16 NCT6775_REG_FAN_STOP_OUTPUT[] = { 0x105, 0x205, 0x305, 0x805, 0x905 }; static const u16 NCT6775_REG_FAN_START_OUTPUT[] = { 0x106, 0x206, 0x306, 0x806, 0x906 }; +static const u16 NCT6775_REG_FAN_STEP_ENABLE[] = { + 0x120, 0x220, 0x320, 0x820, 0x920 }; static const u16 NCT6775_REG_FAN_MAX_OUTPUT[] = { 0x10a, 0x20a, 0x30a }; static const u16 NCT6775_REG_FAN_STEP_OUTPUT[] = { 0x10b, 0x20b, 0x30b }; @@ -305,8 +316,6 @@ static const u16 NCT6776_REG_TEMP_CONFIG[11] static const u16 NCT6779_REG_TEMP_CONFIG[11] = { 0x18, 0x152 }; -static const u16 NCT6775_REG_TEMP_MON[] = { 0x73, 0x75, 0x77, 0x79, 0x7b }; - static const u16 NCT6775_REG_AUTO_TEMP[] = { 0x121, 0x221, 0x321, 0x821, 0x921 }; static const u16 NCT6775_REG_AUTO_PWM[] @@ -564,7 +573,6 @@ struct nct6775_data { */ const u16 *REG_PWM_READ; - const u16 *REG_TEMP_MON; const u16 *REG_AUTO_TEMP; const u16 *REG_AUTO_PWM; @@ -572,7 +580,9 @@ struct nct6775_data { const u16 *REG_CRITICAL_TEMP_TOLERANCE; const u16 *REG_TEMP_SOURCE; /* temp register sources */ - const u16 *REG_TEMP_SEL[2]; /* pwm temp, 0=base, 1=weight */ + const u16 *REG_TEMP_SEL[3]; /* pwm temp: + * 0=base, 1=weight, 2=step enable + */ const u16 *REG_WEIGHT_TEMP[3]; /* 0=base, 1=hyst, 2=step */ @@ -602,7 +612,8 @@ struct nct6775_data { u8 temp_fixed_num; /* 3 or 6 */ u8 temp_type[NUM_TEMP_FIXED]; s8 temp_offset[NUM_TEMP_FIXED]; - s16 temp[3][NUM_TEMP]; /* 0=temp, 1=temp_over, 2=temp_hyst */ + s16 temp[4][NUM_TEMP]; /* 0=temp, 1=temp_over, 2=temp_hyst, + * 3=temp_crit */ u64 alarms; u8 pwm_num; /* number of pwm */ @@ -620,7 +631,6 @@ struct nct6775_data { * [5]=weight_duty_step, [6]=weight_duty_base */ u8 target_temp[5]; - s16 pwm_temp[5]; u8 tolerance[5][2]; u8 fan_time[3][5]; /* 0 = stop_time, 1 = step_up, 2 = step_down */ @@ -632,7 +642,7 @@ struct nct6775_data { u8 pwm_temp_sel[2][5]; - bool pwm_sel_enable[2][5];/* 0->stop_val, 1->weight; + bool pwm_sel_enable[3][5];/* 0->stop_val, 1->weight, 2->step; * false->off, true->on */ u8 weight_temp[3][5]; /* 0->temp_step, 1->temp_step_tol, @@ -777,6 +787,7 @@ static void nct6775_write_fan_div(struct nct6775_data *data, int nr) reg = (nct6775_read_value(data, NCT6775_REG_FANDIV1) & 0x7) | ((data->fan_div[1] << 4) & 0x70); nct6775_write_value(data, NCT6775_REG_FANDIV1, reg); + break; case 2: reg = (nct6775_read_value(data, NCT6775_REG_FANDIV2) & 0x70) | (data->fan_div[2] & 0x7); @@ -861,6 +872,9 @@ static void nct6775_update_pwm(struct device *dev) data->pwm_sel_enable[1][i] = nct6775_read_value(data, data->REG_TEMP_SEL[1][i]) & 0x80; + data->pwm_sel_enable[2][i] = + nct6775_read_value(data, data->REG_TEMP_SEL[2][i]) + & 0x01; /* Weight data */ for (j = 0; j < 2; j++) { @@ -895,8 +909,6 @@ static void nct6775_update_pwm_limits(struct device *dev) data->target_temp[i] = nct6775_read_value(data, data->REG_TARGET[i]) & (data->pwm_mode[i] ? 0xff : 0x7f); - data->pwm_temp[i] = - nct6775_read_value(data, data->REG_TEMP_MON[i]); for (j = 0; j < data->auto_pwm_num; j++) { data->auto_pwm[i][j] = @@ -2116,6 +2128,8 @@ store_pwm_sel_enable(struct device *dev, struct device_attribute *attr, unsigned long val; int err; u8 reg; + static const u8 bit[] = { 0x80, 0x80, 0x01 }; + err = kstrtoul(buf, 10, &val); if (err < 0) @@ -2127,9 +2141,9 @@ store_pwm_sel_enable(struct device *dev, struct device_attribute *attr, mutex_lock(&data->update_lock); data->pwm_sel_enable[index][nr] = val; reg = nct6775_read_value(data, data->REG_TEMP_SEL[index][nr]); - reg &= 0x7f; + reg &= ~bit[index]; if (val) - reg |= 0x80; + reg |= bit[index]; nct6775_write_value(data, data->REG_TEMP_SEL[index][nr], reg); mutex_unlock(&data->update_lock); return count; @@ -2192,6 +2206,17 @@ static SENSOR_DEVICE_ATTR_2(pwm4_weight_enable, S_IWUSR | S_IRUGO, static SENSOR_DEVICE_ATTR_2(pwm5_weight_enable, S_IWUSR | S_IRUGO, show_pwm_sel_enable, store_pwm_sel_enable, 4, 1); +static SENSOR_DEVICE_ATTR_2(pwm1_step_enable, S_IWUSR | S_IRUGO, + show_pwm_sel_enable, store_pwm_sel_enable, 0, 2); +static SENSOR_DEVICE_ATTR_2(pwm2_step_enable, S_IWUSR | S_IRUGO, + show_pwm_sel_enable, store_pwm_sel_enable, 1, 2); +static SENSOR_DEVICE_ATTR_2(pwm3_step_enable, S_IWUSR | S_IRUGO, + show_pwm_sel_enable, store_pwm_sel_enable, 2, 2); +static SENSOR_DEVICE_ATTR_2(pwm4_step_enable, S_IWUSR | S_IRUGO, + show_pwm_sel_enable, store_pwm_sel_enable, 3, 2); +static SENSOR_DEVICE_ATTR_2(pwm5_step_enable, S_IWUSR | S_IRUGO, + show_pwm_sel_enable, store_pwm_sel_enable, 4, 2); + static SENSOR_DEVICE_ATTR_2(pwm1_weight_temp_sel, S_IWUSR | S_IRUGO, show_pwm_temp_sel, store_pwm_temp_sel, 0, 1); static SENSOR_DEVICE_ATTR_2(pwm2_weight_temp_sel, S_IWUSR | S_IRUGO, @@ -2390,13 +2415,14 @@ static struct sensor_device_attribute_2 sda_step_output[] = { 4, 4), }; -static struct attribute *nct6775_attributes_pwm[5][19] = { +static struct attribute *nct6775_attributes_pwm[5][20] = { { &sensor_dev_attr_pwm1.dev_attr.attr, &sensor_dev_attr_pwm1_mode.dev_attr.attr, &sensor_dev_attr_pwm1_enable.dev_attr.attr, &sensor_dev_attr_pwm1_stop_output_enable.dev_attr.attr, &sensor_dev_attr_pwm1_weight_enable.dev_attr.attr, + &sensor_dev_attr_pwm1_step_enable.dev_attr.attr, &sensor_dev_attr_pwm1_temp_sel.dev_attr.attr, &sensor_dev_attr_pwm1_target.dev_attr.attr, &sensor_dev_attr_pwm1_stop_time.dev_attr.attr, @@ -2417,6 +2443,7 @@ static struct attribute *nct6775_attributes_pwm[5][19] = { &sensor_dev_attr_pwm2_enable.dev_attr.attr, &sensor_dev_attr_pwm2_stop_output_enable.dev_attr.attr, &sensor_dev_attr_pwm2_weight_enable.dev_attr.attr, + &sensor_dev_attr_pwm2_step_enable.dev_attr.attr, &sensor_dev_attr_pwm2_temp_sel.dev_attr.attr, &sensor_dev_attr_pwm2_target.dev_attr.attr, &sensor_dev_attr_pwm2_stop_time.dev_attr.attr, @@ -2437,6 +2464,7 @@ static struct attribute *nct6775_attributes_pwm[5][19] = { &sensor_dev_attr_pwm3_enable.dev_attr.attr, &sensor_dev_attr_pwm3_stop_output_enable.dev_attr.attr, &sensor_dev_attr_pwm3_weight_enable.dev_attr.attr, + &sensor_dev_attr_pwm3_step_enable.dev_attr.attr, &sensor_dev_attr_pwm3_temp_sel.dev_attr.attr, &sensor_dev_attr_pwm3_target.dev_attr.attr, &sensor_dev_attr_pwm3_stop_time.dev_attr.attr, @@ -2457,6 +2485,7 @@ static struct attribute *nct6775_attributes_pwm[5][19] = { &sensor_dev_attr_pwm4_enable.dev_attr.attr, &sensor_dev_attr_pwm4_stop_output_enable.dev_attr.attr, &sensor_dev_attr_pwm4_weight_enable.dev_attr.attr, + &sensor_dev_attr_pwm4_step_enable.dev_attr.attr, &sensor_dev_attr_pwm4_temp_sel.dev_attr.attr, &sensor_dev_attr_pwm4_target.dev_attr.attr, &sensor_dev_attr_pwm4_stop_time.dev_attr.attr, @@ -2477,6 +2506,7 @@ static struct attribute *nct6775_attributes_pwm[5][19] = { &sensor_dev_attr_pwm5_enable.dev_attr.attr, &sensor_dev_attr_pwm5_stop_output_enable.dev_attr.attr, &sensor_dev_attr_pwm5_weight_enable.dev_attr.attr, + &sensor_dev_attr_pwm5_step_enable.dev_attr.attr, &sensor_dev_attr_pwm5_temp_sel.dev_attr.attr, &sensor_dev_attr_pwm5_target.dev_attr.attr, &sensor_dev_attr_pwm5_stop_time.dev_attr.attr, @@ -2862,6 +2892,7 @@ clear_caseopen(struct device *dev, struct device_attribute *attr, int nr = to_sensor_dev_attr(attr)->index - INTRUSION_ALARM_BASE; unsigned long val; u8 reg; + int ret; if (kstrtoul(buf, 10, &val) || val != 0) return -EINVAL; @@ -2873,7 +2904,12 @@ clear_caseopen(struct device *dev, struct device_attribute *attr, * The CR registers are the same for all chips, and not all chips * support clearing the caseopen status through "regular" registers. */ - superio_enter(sio_data->sioreg); + ret = superio_enter(sio_data->sioreg); + if (ret) { + count = ret; + goto error; + } + superio_select(sio_data->sioreg, NCT6775_LD_ACPI); reg = superio_inb(sio_data->sioreg, NCT6775_REG_CR_CASEOPEN_CLR[nr]); reg |= NCT6775_CR_CASEOPEN_CLR_MASK[nr]; @@ -2883,9 +2919,8 @@ clear_caseopen(struct device *dev, struct device_attribute *attr, superio_exit(sio_data->sioreg); data->valid = 0; /* Force cache refresh */ - +error: mutex_unlock(&data->update_lock); - return count; } @@ -2999,15 +3034,18 @@ static inline void __devinit nct6775_init_device(struct nct6775_data *data) } } -static void __devinit +static int __devinit nct6775_check_fan_inputs(const struct nct6775_sio_data *sio_data, struct nct6775_data *data) { int regval; bool fan3pin, fan3min, fan4pin, fan4min, fan5pin; bool pwm3pin, pwm4pin, pwm5pin; + int ret; - superio_enter(sio_data->sioreg); + ret = superio_enter(sio_data->sioreg); + if (ret) + return ret; /* fan4 and fan5 share some pins with the GPIO and serial flash */ if (data->kind == nct6775) { @@ -3074,6 +3112,8 @@ nct6775_check_fan_inputs(const struct nct6775_sio_data *sio_data, data->has_fan_min |= (fan4min << 3) | (fan5pin << 4); data->has_pwm = 0x03 | (pwm3pin << 2) | (pwm4pin << 3) | (pwm5pin << 4); + + return 0; } static int __devinit nct6775_probe(struct platform_device *pdev) @@ -3143,7 +3183,6 @@ static int __devinit nct6775_probe(struct platform_device *pdev) data->REG_PWM_READ = NCT6775_REG_PWM_READ; data->REG_PWM_MODE = NCT6775_REG_PWM_MODE; data->PWM_MODE_MASK = NCT6775_PWM_MODE_MASK; - data->REG_TEMP_MON = NCT6775_REG_TEMP_MON; data->REG_AUTO_TEMP = NCT6775_REG_AUTO_TEMP; data->REG_AUTO_PWM = NCT6775_REG_AUTO_PWM; data->REG_CRITICAL_TEMP = NCT6775_REG_CRITICAL_TEMP; @@ -3153,6 +3192,7 @@ static int __devinit nct6775_probe(struct platform_device *pdev) data->REG_TEMP_SOURCE = NCT6775_REG_TEMP_SOURCE; data->REG_TEMP_SEL[0] = NCT6775_REG_TEMP_SEL; data->REG_TEMP_SEL[1] = NCT6775_REG_WEIGHT_TEMP_SEL; + data->REG_TEMP_SEL[2] = NCT6775_REG_FAN_STEP_ENABLE; data->REG_WEIGHT_TEMP[0] = NCT6775_REG_WEIGHT_TEMP_STEP; data->REG_WEIGHT_TEMP[1] = NCT6775_REG_WEIGHT_TEMP_STEP_TOL; data->REG_WEIGHT_TEMP[2] = NCT6775_REG_WEIGHT_TEMP_BASE; @@ -3203,7 +3243,6 @@ static int __devinit nct6775_probe(struct platform_device *pdev) data->REG_PWM_READ = NCT6775_REG_PWM_READ; data->REG_PWM_MODE = NCT6776_REG_PWM_MODE; data->PWM_MODE_MASK = NCT6776_PWM_MODE_MASK; - data->REG_TEMP_MON = NCT6775_REG_TEMP_MON; data->REG_AUTO_TEMP = NCT6775_REG_AUTO_TEMP; data->REG_AUTO_PWM = NCT6775_REG_AUTO_PWM; data->REG_CRITICAL_TEMP = NCT6775_REG_CRITICAL_TEMP; @@ -3213,6 +3252,7 @@ static int __devinit nct6775_probe(struct platform_device *pdev) data->REG_TEMP_SOURCE = NCT6775_REG_TEMP_SOURCE; data->REG_TEMP_SEL[0] = NCT6775_REG_TEMP_SEL; data->REG_TEMP_SEL[1] = NCT6775_REG_WEIGHT_TEMP_SEL; + data->REG_TEMP_SEL[2] = NCT6775_REG_FAN_STEP_ENABLE; data->REG_WEIGHT_TEMP[0] = NCT6775_REG_WEIGHT_TEMP_STEP; data->REG_WEIGHT_TEMP[1] = NCT6775_REG_WEIGHT_TEMP_STEP_TOL; data->REG_WEIGHT_TEMP[2] = NCT6775_REG_WEIGHT_TEMP_BASE; @@ -3263,7 +3303,6 @@ static int __devinit nct6775_probe(struct platform_device *pdev) data->REG_PWM_READ = NCT6775_REG_PWM_READ; data->REG_PWM_MODE = NCT6776_REG_PWM_MODE; data->PWM_MODE_MASK = NCT6776_PWM_MODE_MASK; - data->REG_TEMP_MON = NCT6775_REG_TEMP_MON; data->REG_AUTO_TEMP = NCT6775_REG_AUTO_TEMP; data->REG_AUTO_PWM = NCT6775_REG_AUTO_PWM; data->REG_CRITICAL_TEMP = NCT6775_REG_CRITICAL_TEMP; @@ -3273,6 +3312,7 @@ static int __devinit nct6775_probe(struct platform_device *pdev) data->REG_TEMP_SOURCE = NCT6775_REG_TEMP_SOURCE; data->REG_TEMP_SEL[0] = NCT6775_REG_TEMP_SEL; data->REG_TEMP_SEL[1] = NCT6775_REG_WEIGHT_TEMP_SEL; + data->REG_TEMP_SEL[2] = NCT6775_REG_FAN_STEP_ENABLE; data->REG_WEIGHT_TEMP[0] = NCT6775_REG_WEIGHT_TEMP_STEP; data->REG_WEIGHT_TEMP[1] = NCT6775_REG_WEIGHT_TEMP_STEP_TOL; data->REG_WEIGHT_TEMP[2] = NCT6775_REG_WEIGHT_TEMP_BASE; @@ -3473,7 +3513,10 @@ static int __devinit nct6775_probe(struct platform_device *pdev) nct6775_init_device(data); data->vrm = vid_which_vrm(); - superio_enter(sio_data->sioreg); + err = superio_enter(sio_data->sioreg); + if (err) + return err; + /* * Read VID value * We can get the VID input values directly at logical device D 0xe3. @@ -3508,7 +3551,9 @@ static int __devinit nct6775_probe(struct platform_device *pdev) if (err) return err; - nct6775_check_fan_inputs(sio_data, data); + err = nct6775_check_fan_inputs(sio_data, data); + if (err) + goto exit_remove; /* Read fan clock dividers immediately */ nct6775_update_fan_div_common(dev, data); @@ -3682,14 +3727,17 @@ static struct platform_driver nct6775_driver = { static int __init nct6775_find(int sioaddr, unsigned short *addr, struct nct6775_sio_data *sio_data) { - static const char __initdata sio_name_NCT6775[] = "NCT6775F"; - static const char __initdata sio_name_NCT6776[] = "NCT6776F"; - static const char __initdata sio_name_NCT6779[] = "NCT6779D"; + static const char sio_name_NCT6775[] __initconst = "NCT6775F"; + static const char sio_name_NCT6776[] __initconst = "NCT6776F"; + static const char sio_name_NCT6779[] __initconst = "NCT6779D"; u16 val; const char *sio_name; + int err; - superio_enter(sioaddr); + err = superio_enter(sioaddr); + if (err) + return err; if (force_id) val = force_id;