X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=post%2Fcpu%2Fppc4xx%2Fdenali_ecc.c;h=1190739ae1a90964523b6964fcc8edcd7269af80;hb=54a0eb7a18b5120d609188e46a1b71e98d6af44b;hp=439f80d1f6586132799945e393a9f87ccaa85ec3;hpb=8d54477b9bfc666632e767946ea190fc6ce52775;p=u-boot

diff --git a/post/cpu/ppc4xx/denali_ecc.c b/post/cpu/ppc4xx/denali_ecc.c
index 439f80d1f6..1190739ae1 100644
--- a/post/cpu/ppc4xx/denali_ecc.c
+++ b/post/cpu/ppc4xx/denali_ecc.c
@@ -4,23 +4,7 @@
  *
  * Author: Pavel Kolesnikov <concord@emcraft.com>
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:	GPL-2.0+
  */
 
 /* define DEBUG for debugging output (obviously ;-)) */
@@ -31,11 +15,11 @@
 #include <common.h>
 #include <watchdog.h>
 
-#if defined(CONFIG_POST) && (defined(CONFIG_440EPX) || defined(CONFIG_440GRX))
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 
 #include <post.h>
 
-#if CONFIG_POST & CFG_POST_ECC
+#if CONFIG_POST & CONFIG_SYS_POST_ECC
 
 /*
  * MEMORY ECC test
@@ -45,7 +29,7 @@
 #include <asm/processor.h>
 #include <asm/mmu.h>
 #include <asm/io.h>
-#include <ppc440.h>
+#include <asm/ppc440.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -174,6 +158,7 @@ static int test_ecc(uint32_t ecc_addr)
 	clear_and_enable_ecc();
 	out_be32(ecc_mem, ECC_PATTERN);
 	out_be32(ecc_mem + 1, ECC_PATTERN);
+	ppcDcbf((u32)ecc_mem);
 
 	/* Verify no ECC error reading back */
 	value = in_be32(ecc_mem);
@@ -193,6 +178,7 @@ static int test_ecc(uint32_t ecc_addr)
 
 	/* Test for correctable error by creating a one-bit error */
 	out_be32(ecc_mem, ECC_PATTERN_CORR);
+	ppcDcbf((u32)ecc_mem);
 	clear_and_enable_ecc();
 	value = in_be32(ecc_mem);
 	disable_ecc();
@@ -212,6 +198,7 @@ static int test_ecc(uint32_t ecc_addr)
 
 	/* Test for uncorrectable error by creating a two-bit error */
 	out_be32(ecc_mem, ECC_PATTERN_UNCORR);
+	ppcDcbf((u32)ecc_mem);
 	clear_and_enable_ecc();
 	value = in_be32(ecc_mem);
 	disable_ecc();
@@ -232,6 +219,7 @@ static int test_ecc(uint32_t ecc_addr)
 
 	/* Remove error from SDRAM and enable ECC. */
 	out_be32(ecc_mem, ECC_PATTERN);
+	ppcDcbf((u32)ecc_mem);
 	clear_and_enable_ecc();
 
 	return ret;
@@ -267,5 +255,5 @@ int ecc_post_test(int flags)
 	debug("ecc_post_test() returning %d\n", ret);
 	return ret;
 }
-#endif /* CONFIG_POST & CFG_POST_ECC */
-#endif /* defined(CONFIG_POST) && ... */
+#endif /* CONFIG_POST & CONFIG_SYS_POST_ECC */
+#endif /* defined(CONFIG_440EPX) || defined(CONFIG_440GRX) */