X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=post%2Fcpu%2Fppc4xx%2Fether.c;h=8a4c56b7d622ead7495710294a3a64b69a88b352;hb=54a0eb7a18b5120d609188e46a1b71e98d6af44b;hp=c3665da94a6ffbc8af0d8f749263387b2dcbc491;hpb=d1c3b27525b664e8c4db6bb173eed51bfc8220de;p=u-boot diff --git a/post/cpu/ppc4xx/ether.c b/post/cpu/ppc4xx/ether.c index c3665da94a..8a4c56b7d6 100644 --- a/post/cpu/ppc4xx/ether.c +++ b/post/cpu/ppc4xx/ether.c @@ -4,23 +4,7 @@ * * Author: Igor Lisitsin * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0+ */ #include @@ -34,7 +18,10 @@ * are transmitted. The configurable test parameters are: * MIN_PACKET_LENGTH - minimum size of packet to transmit * MAX_PACKET_LENGTH - maximum size of packet to transmit - * TEST_NUM - number of tests + * CONFIG_SYS_POST_ETH_LOOPS - Number of test loops. Each loop + * is tested with a different frame length. Starting with + * MAX_PACKET_LENGTH and going down to MIN_PACKET_LENGTH. + * Defaults to 10 and can be overridden in the board config header. */ #include @@ -44,8 +31,8 @@ #include #include #include -#include <405_mal.h> -#include +#include +#include #include DECLARE_GLOBAL_DATA_PTR; @@ -77,8 +64,12 @@ DECLARE_GLOBAL_DATA_PTR; #endif #define MIN_PACKET_LENGTH 64 -#define MAX_PACKET_LENGTH 256 -#define TEST_NUM 1 +#define MAX_PACKET_LENGTH 1514 +#ifndef CONFIG_SYS_POST_ETH_LOOPS +#define CONFIG_SYS_POST_ETH_LOOPS 10 +#endif +#define PACKET_INCR ((MAX_PACKET_LENGTH - MIN_PACKET_LENGTH) / \ + CONFIG_SYS_POST_ETH_LOOPS) static volatile mal_desc_t tx __cacheline_aligned; static volatile mal_desc_t rx __cacheline_aligned; @@ -115,11 +106,11 @@ static void ether_post_init (int devnum, int hw_addr) sync (); #endif /* reset emac */ - out_be32 ((void*)(EMAC_M0 + hw_addr), EMAC_M0_SRST); + out_be32 ((void*)(EMAC0_MR0 + hw_addr), EMAC_MR0_SRST); sync (); for (i = 0;; i++) { - if (!(in_be32 ((void*)(EMAC_M0 + hw_addr)) & EMAC_M0_SRST)) + if (!(in_be32 ((void*)(EMAC0_MR0 + hw_addr)) & EMAC_MR0_SRST)) break; if (i >= 1000) { printf ("Timeout resetting EMAC\n"); @@ -134,15 +125,15 @@ static void ether_post_init (int devnum, int hw_addr) mode_reg = 0x0; if (sysinfo.freqOPB <= 50000000); else if (sysinfo.freqOPB <= 66666667) - mode_reg |= EMAC_M1_OBCI_66; + mode_reg |= EMAC_MR1_OBCI_66; else if (sysinfo.freqOPB <= 83333333) - mode_reg |= EMAC_M1_OBCI_83; + mode_reg |= EMAC_MR1_OBCI_83; else if (sysinfo.freqOPB <= 100000000) - mode_reg |= EMAC_M1_OBCI_100; + mode_reg |= EMAC_MR1_OBCI_100; else - mode_reg |= EMAC_M1_OBCI_GT100; + mode_reg |= EMAC_MR1_OBCI_GT100; - out_be32 ((void*)(EMAC_M1 + hw_addr), mode_reg); + out_be32 ((void*)(EMAC0_MR1 + hw_addr), mode_reg); #endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */ @@ -210,40 +201,40 @@ static void ether_post_init (int devnum, int hw_addr) /* set internal loopback mode */ #ifdef CONFIG_SYS_POST_ETHER_EXT_LOOPBACK - out_be32 ((void*)(EMAC_M1 + hw_addr), EMAC_M1_FDE | 0 | - EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K | - EMAC_M1_MF_100MBPS | EMAC_M1_IST | - in_be32 ((void*)(EMAC_M1 + hw_addr))); + out_be32 ((void*)(EMAC0_MR1 + hw_addr), EMAC_MR1_FDE | 0 | + EMAC_MR1_RFS_4K | EMAC_MR1_TX_FIFO_2K | + EMAC_MR1_MF_100MBPS | EMAC_MR1_IST | + in_be32 ((void*)(EMAC0_MR1 + hw_addr))); #else - out_be32 ((void*)(EMAC_M1 + hw_addr), EMAC_M1_FDE | EMAC_M1_ILE | - EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K | - EMAC_M1_MF_100MBPS | EMAC_M1_IST | - in_be32 ((void*)(EMAC_M1 + hw_addr))); + out_be32 ((void*)(EMAC0_MR1 + hw_addr), EMAC_MR1_FDE | EMAC_MR1_ILE | + EMAC_MR1_RFS_4K | EMAC_MR1_TX_FIFO_2K | + EMAC_MR1_MF_100MBPS | EMAC_MR1_IST | + in_be32 ((void*)(EMAC0_MR1 + hw_addr))); #endif /* set transmit enable & receive enable */ - out_be32 ((void*)(EMAC_M0 + hw_addr), EMAC_M0_TXE | EMAC_M0_RXE); + out_be32 ((void*)(EMAC0_MR0 + hw_addr), EMAC_MR0_TXE | EMAC_MR0_RXE); /* enable broadcast address */ - out_be32 ((void*)(EMAC_RXM + hw_addr), EMAC_RMR_BAE); + out_be32 ((void*)(EMAC0_RXM + hw_addr), EMAC_RMR_BAE); /* set transmit request threshold register */ - out_be32 ((void*)(EMAC_TRTR + hw_addr), 0x18000000); /* 256 byte threshold */ + out_be32 ((void*)(EMAC0_TRTR + hw_addr), 0x18000000); /* 256 byte threshold */ /* set receive low/high water mark register */ #if defined(CONFIG_440) /* 440s has a 64 byte burst length */ - out_be32 ((void*)(EMAC_RX_HI_LO_WMARK + hw_addr), 0x80009000); + out_be32 ((void*)(EMAC0_RX_HI_LO_WMARK + hw_addr), 0x80009000); #else /* 405s have a 16 byte burst length */ - out_be32 ((void*)(EMAC_RX_HI_LO_WMARK + hw_addr), 0x0f002000); + out_be32 ((void*)(EMAC0_RX_HI_LO_WMARK + hw_addr), 0x0f002000); #endif /* defined(CONFIG_440) */ - out_be32 ((void*)(EMAC_TXM1 + hw_addr), 0xf8640000); + out_be32 ((void*)(EMAC0_TMR1 + hw_addr), 0xf8640000); /* Set fifo limit entry in tx mode 0 */ - out_be32 ((void*)(EMAC_TXM0 + hw_addr), 0x00000003); + out_be32 ((void*)(EMAC0_TMR0 + hw_addr), 0x00000003); /* Frame gap set */ - out_be32 ((void*)(EMAC_I_FRAME_GAP_REG + hw_addr), 0x00000008); + out_be32 ((void*)(EMAC0_I_FRAME_GAP_REG + hw_addr), 0x00000008); sync (); } @@ -270,7 +261,7 @@ static void ether_post_halt (int devnum, int hw_addr) udelay (1000); } /* emac reset */ - out_be32 ((void*)(EMAC_M0 + hw_addr), EMAC_M0_SRST); + out_be32 ((void*)(EMAC0_MR0 + hw_addr), EMAC_MR0_SRST); #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX) /* remove clocks for EMAC internal loopback */ @@ -300,7 +291,7 @@ static void ether_post_send (int devnum, int hw_addr, void *packet, int length) flush_dcache_range((u32)tx.data_ptr, (u32)tx.data_ptr + length); sync (); - out_be32 ((void*)(EMAC_TXM0 + hw_addr), in_be32 ((void*)(EMAC_TXM0 + hw_addr)) | EMAC_TXM0_GNP0); + out_be32 ((void*)(EMAC0_TMR0 + hw_addr), in_be32 ((void*)(EMAC0_TMR0 + hw_addr)) | EMAC_TMR0_GNP0); sync (); } @@ -361,29 +352,27 @@ static int packet_check (char *packet, int length) return 0; } + char packet_send[MAX_PACKET_LENGTH]; + char packet_recv[MAX_PACKET_LENGTH]; static int test_ctlr (int devnum, int hw_addr) { int res = -1; - char packet_send[MAX_PACKET_LENGTH]; - char packet_recv[MAX_PACKET_LENGTH]; int length; - int i; int l; ether_post_init (devnum, hw_addr); - for (i = 0; i < TEST_NUM; i++) { - for (l = MIN_PACKET_LENGTH; l <= MAX_PACKET_LENGTH; l++) { - packet_fill (packet_send, l); + for (l = MAX_PACKET_LENGTH; l >= MIN_PACKET_LENGTH; + l -= PACKET_INCR) { + packet_fill (packet_send, l); - ether_post_send (devnum, hw_addr, packet_send, l); + ether_post_send (devnum, hw_addr, packet_send, l); - length = ether_post_recv (devnum, hw_addr, packet_recv, - sizeof (packet_recv)); + length = ether_post_recv (devnum, hw_addr, packet_recv, + sizeof (packet_recv)); - if (length != l || packet_check (packet_recv, length) < 0) { - goto Done; - } + if (length != l || packet_check (packet_recv, length) < 0) { + goto Done; } }