X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=post%2Fcpu%2Fppc4xx%2Ffpu.c;h=9f496906d223fa072c8c020838dc7a447f668da6;hb=b36df561154bdd0a41bb77e09c5575ca2cf48013;hp=c2eb4a9bf0b5e03c4a0dc7bba7284b3ebc2ad884;hpb=0459e7d3a0a273064b738aa2e06fd7dcd35eec58;p=u-boot

diff --git a/post/cpu/ppc4xx/fpu.c b/post/cpu/ppc4xx/fpu.c
index c2eb4a9bf0..9f496906d2 100644
--- a/post/cpu/ppc4xx/fpu.c
+++ b/post/cpu/ppc4xx/fpu.c
@@ -25,35 +25,33 @@
 
 #include <config.h>
 
-#ifdef CONFIG_POST
 #if defined(CONFIG_440EP) || \
     defined(CONFIG_440EPX)
 
-#include <ppc4xx.h>
 #include <asm/processor.h>
+#include <asm/ppc4xx.h>
 
 
 int fpu_status(void)
 {
-	if (mfspr(ccr0) & CCR0_DAPUIB)
+	if (mfspr(SPRN_CCR0) & CCR0_DAPUIB)
 		return 0; /* Disabled */
-	else 
+	else
 		return 1; /* Enabled */
 }
 
 
 void fpu_disable(void)
 {
-	mtspr(ccr0, mfspr(ccr0) | CCR0_DAPUIB);
+	mtspr(SPRN_CCR0, mfspr(SPRN_CCR0) | CCR0_DAPUIB);
 	mtmsr(mfmsr() & ~MSR_FP);
 }
 
 
 void fpu_enable(void)
 {
-	mtspr(ccr0, mfspr(ccr0) & ~CCR0_DAPUIB);
+	mtspr(SPRN_CCR0, mfspr(SPRN_CCR0) & ~CCR0_DAPUIB);
 	mtmsr(mfmsr() | MSR_FP);
 }
 
 #endif
-#endif /* CONFIG_POST */