X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=post%2Fdrivers%2Fmemory.c;h=c2b711e2f4100aeb43cd30eb5dadc2ff024f87e5;hb=310ae55efe14aa7923b16c718cbdb22ec364b18b;hp=006236009917e7f912d8ddee0efca2e7c0759573;hpb=f82642e33899766892499b163e60560fbbf87773;p=u-boot

diff --git a/post/drivers/memory.c b/post/drivers/memory.c
index 0062360099..c2b711e2f4 100644
--- a/post/drivers/memory.c
+++ b/post/drivers/memory.c
@@ -225,7 +225,7 @@ const unsigned long long otherpattern = 0x0123456789abcdefULL;
 static int memory_post_dataline(unsigned long long * pmem)
 {
 	unsigned long long temp64 = 0;
-	int num_patterns = sizeof(pattern)/ sizeof(pattern[0]);
+	int num_patterns = ARRAY_SIZE(pattern);
 	int i;
 	unsigned int hi, lo, pathi, patlo;
 	int ret = 0;
@@ -452,30 +452,71 @@ static int memory_post_tests (unsigned long start, unsigned long size)
 	return ret;
 }
 
-int memory_post_test (int flags)
+/*
+ * !! this is only valid, if you have contiguous memory banks !!
+ */
+__attribute__((weak))
+int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
 {
-	int ret = 0;
 	bd_t *bd = gd->bd;
-	unsigned long memsize = (bd->bi_memsize >= 256 << 20 ?
-				 256 << 20 : bd->bi_memsize) - (1 << 20);
+
+	*vstart = CONFIG_SYS_SDRAM_BASE;
+	*size = (gd->ram_size >= 256 << 20 ?
+			256 << 20 : gd->ram_size) - (1 << 20);
 
 	/* Limit area to be tested with the board info struct */
-	if (CONFIG_SYS_SDRAM_BASE + memsize > (ulong)bd)
-		memsize = (ulong)bd - CONFIG_SYS_SDRAM_BASE;
+	if ((*vstart) + (*size) > (ulong)bd)
+		*size = (ulong)bd - *vstart;
+
+	return 0;
+}
+
+__attribute__((weak))
+int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
+{
+	return 1;
+}
 
-	if (flags & POST_SLOWTEST) {
-		ret = memory_post_tests (CONFIG_SYS_SDRAM_BASE, memsize);
-	} else {			/* POST_NORMAL */
+__attribute__((weak))
+int arch_memory_test_cleanup(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
+{
+	return 0;
+}
 
-		unsigned long i;
+__attribute__((weak))
+void arch_memory_failure_handle(void)
+{
+	return;
+}
 
-		for (i = 0; i < (memsize >> 20) && ret == 0; i++) {
-			if (ret == 0)
-				ret = memory_post_tests (i << 20, 0x800);
-			if (ret == 0)
-				ret = memory_post_tests ((i << 20) + 0xff800, 0x800);
+int memory_post_test(int flags)
+{
+	int ret = 0;
+	phys_addr_t phys_offset = 0;
+	u32 memsize, vstart;
+
+	arch_memory_test_prepare(&vstart, &memsize, &phys_offset);
+
+	do {
+		if (flags & POST_SLOWTEST) {
+			ret = memory_post_tests(vstart, memsize);
+		} else {			/* POST_NORMAL */
+			unsigned long i;
+			for (i = 0; i < (memsize >> 20) && ret == 0; i++) {
+				if (ret == 0)
+					ret = memory_post_tests(vstart +
+						(i << 20), 0x800);
+				if (ret == 0)
+					ret = memory_post_tests(vstart +
+						(i << 20) + 0xff800, 0x800);
+			}
 		}
-	}
+	} while (!ret &&
+		!arch_memory_test_advance(&vstart, &memsize, &phys_offset));
+
+	arch_memory_test_cleanup(&vstart, &memsize, &phys_offset);
+	if (ret)
+		arch_memory_failure_handle();
 
 	return ret;
 }