X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=post%2Flib_ppc%2Fandi.c;h=52ec7c4d4e919c384bd3b62e3a9636d3399d34e2;hb=3adc1fda38a6aacd4aaf3c2c9cc62a1e69e6de17;hp=7ddf2ab2f3bc01c2dc5aa66d294478d5a8038817;hpb=ee89bf2782406b1f87088b4764aeb6f811d82526;p=u-boot

diff --git a/post/lib_ppc/andi.c b/post/lib_ppc/andi.c
index 7ddf2ab2f3..52ec7c4d4e 100644
--- a/post/lib_ppc/andi.c
+++ b/post/lib_ppc/andi.c
@@ -32,12 +32,10 @@
  * different sets of operand registers and result registers.
  */
 
-#ifdef CONFIG_POST
-
 #include <post.h>
 #include "cpu_asm.h"
 
-#if CONFIG_POST & CFG_POST_CPU
+#if CONFIG_POST & CONFIG_SYS_POST_CPU
 
 extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op);
 extern ulong cpu_post_makecr (long v);
@@ -51,13 +49,13 @@ static struct cpu_post_andi_s
 } cpu_post_andi_table[] =
 {
     {
-    	OP_ANDI_,
+	OP_ANDI_,
 	0x80008000,
 	0xffff,
 	0x00008000
     },
     {
-    	OP_ANDIS_,
+	OP_ANDIS_,
 	0x80008000,
 	0xffff,
 	0x80000000
@@ -81,7 +79,7 @@ int cpu_post_test_andi (void)
 	    unsigned int reg0 = (reg + 0) % 32;
 	    unsigned int reg1 = (reg + 1) % 32;
 	    unsigned int stk = reg < 16 ? 31 : 15;
-    	    unsigned long codecr[] =
+	    unsigned long codecr[] =
 	    {
 		ASM_STW(stk, 1, -4),
 		ASM_ADDI(stk, 1, -16),
@@ -114,10 +112,9 @@ int cpu_post_test_andi (void)
     }
 
     if (flag)
-    	enable_interrupts();
+	enable_interrupts();
 
     return ret;
 }
 
 #endif
-#endif