X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=post%2Flib_ppc%2Fthreei.c;h=31953f93543498f1f9d84748001c16ca947af5d5;hb=e4430779623af500de1cee7892c379f07ef59813;hp=79f01789c00e36e4cff93c066b9903a91d1d125e;hpb=19bf91f9628f80a55d4f171df71041574882b3d6;p=u-boot

diff --git a/post/lib_ppc/threei.c b/post/lib_ppc/threei.c
index 79f01789c0..31953f9354 100644
--- a/post/lib_ppc/threei.c
+++ b/post/lib_ppc/threei.c
@@ -34,12 +34,10 @@
  * different sets of operand registers and result registers.
  */
 
-#ifdef CONFIG_POST
-
 #include <post.h>
 #include "cpu_asm.h"
 
-#if CONFIG_POST & CFG_POST_CPU
+#if CONFIG_POST & CONFIG_SYS_POST_CPU
 
 extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op);
 extern ulong cpu_post_makecr (long v);
@@ -53,25 +51,25 @@ static struct cpu_post_threei_s
 } cpu_post_threei_table[] =
 {
     {
-    	OP_ORI,
+	OP_ORI,
 	0x80000000,
 	0xffff,
 	0x8000ffff
     },
     {
-    	OP_ORIS,
+	OP_ORIS,
 	0x00008000,
 	0xffff,
 	0xffff8000
     },
     {
-    	OP_XORI,
+	OP_XORI,
 	0x8000ffff,
 	0xffff,
 	0x80000000
     },
     {
-    	OP_XORIS,
+	OP_XORIS,
 	0x00008000,
 	0xffff,
 	0xffff8000
@@ -95,7 +93,7 @@ int cpu_post_test_threei (void)
 	    unsigned int reg0 = (reg + 0) % 32;
 	    unsigned int reg1 = (reg + 1) % 32;
 	    unsigned int stk = reg < 16 ? 31 : 15;
-    	    unsigned long code[] =
+	    unsigned long code[] =
 	    {
 		ASM_STW(stk, 1, -4),
 		ASM_ADDI(stk, 1, -16),
@@ -115,7 +113,7 @@ int cpu_post_test_threei (void)
 	    ulong res;
 	    ulong cr;
 
- 	    cr = 0;
+	    cr = 0;
 	    cpu_post_exec_21 (code, & cr, & res, test->op1);
 
 	    ret = res == test->res && cr == 0 ? 0 : -1;
@@ -128,10 +126,9 @@ int cpu_post_test_threei (void)
     }
 
     if (flag)
-    	enable_interrupts();
+	enable_interrupts();
 
     return ret;
 }
 
 #endif
-#endif