X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=post%2Fspr.c;h=330b977f1a56e4256028cf3bf42423f543175a14;hb=8bde7f776c77b343aca29b8c7b58464d915ac245;hp=97f761062f179b28cd02450e3ea94aaafd678a1d;hpb=993cad9364c6b87ae429d1ed1130d8153f6f027e;p=u-boot

diff --git a/post/spr.c b/post/spr.c
index 97f761062f..330b977f1a 100644
--- a/post/spr.c
+++ b/post/spr.c
@@ -48,66 +48,66 @@ static struct
 } spr_test_list [] = {
 	/* Standard Special-Purpose Registers */
 
-        {1,	"XER",		0x00000000,	0x00000000},
-        {8,	"LR",		0x00000000,	0x00000000},
-        {9,	"CTR",		0x00000000,	0x00000000},
-        {18,	"DSISR",	0x00000000,	0x00000000},
-        {19,	"DAR",		0x00000000,	0x00000000},
-        {22,	"DEC",		0x00000000,	0x00000000},
-        {26,	"SRR0",		0x00000000,	0x00000000},
-        {27,	"SRR1",		0x00000000,	0x00000000},
-        {272,	"SPRG0",	0x00000000,	0x00000000},
-        {273,	"SPRG1",	0x00000000,	0x00000000},
-        {274,	"SPRG2",	0x00000000,	0x00000000},
-        {275,	"SPRG3",	0x00000000,	0x00000000},
-        {287,	"PVR",		0xFFFF0000,	0x00500000},
+	{1,	"XER",		0x00000000,	0x00000000},
+	{8,	"LR",		0x00000000,	0x00000000},
+	{9,	"CTR",		0x00000000,	0x00000000},
+	{18,	"DSISR",	0x00000000,	0x00000000},
+	{19,	"DAR",		0x00000000,	0x00000000},
+	{22,	"DEC",		0x00000000,	0x00000000},
+	{26,	"SRR0",		0x00000000,	0x00000000},
+	{27,	"SRR1",		0x00000000,	0x00000000},
+	{272,	"SPRG0",	0x00000000,	0x00000000},
+	{273,	"SPRG1",	0x00000000,	0x00000000},
+	{274,	"SPRG2",	0x00000000,	0x00000000},
+	{275,	"SPRG3",	0x00000000,	0x00000000},
+	{287,	"PVR",		0xFFFF0000,	0x00500000},
 
 	/* Additional Special-Purpose Registers */
 
-        {144,	"CMPA",		0x00000000,	0x00000000},
-        {145,	"CMPB",		0x00000000,	0x00000000},
-        {146,	"CMPC",		0x00000000,	0x00000000},
-        {147,	"CMPD",		0x00000000,	0x00000000},
-        {148,	"ICR",		0xFFFFFFFF,	0x00000000},
-        {149,	"DER",		0x00000000,	0x00000000},
-        {150,	"COUNTA",	0xFFFFFFFF,	0x00000000},
-        {151,	"COUNTB",	0xFFFFFFFF,	0x00000000},
-        {152,	"CMPE",		0x00000000,	0x00000000},
-        {153,	"CMPF",		0x00000000,	0x00000000},
-        {154,	"CMPG",		0x00000000,	0x00000000},
-        {155,	"CMPH",		0x00000000,	0x00000000},
-        {156,	"LCTRL1",	0xFFFFFFFF,	0x00000000},
-        {157,	"LCTRL2",	0xFFFFFFFF,	0x00000000},
-        {158,	"ICTRL",	0xFFFFFFFF,	0x00000007},
-        {159,	"BAR",		0x00000000,	0x00000000},
-        {630,	"DPDR",		0x00000000,	0x00000000},
-        {631,	"DPIR",		0x00000000,	0x00000000},
-        {638,	"IMMR",		0xFFFF0000,	CFG_IMMR  },
-        {560,	"IC_CST",	0x8E380000,	0x00000000},
-        {561,	"IC_ADR",	0x00000000,	0x00000000},
-        {562,	"IC_DAT",	0x00000000,	0x00000000},
-        {568,	"DC_CST",	0xEF380000,	0x00000000},
-        {569,	"DC_ADR",	0x00000000,	0x00000000},
-        {570,	"DC_DAT",	0x00000000,	0x00000000},
-        {784,	"MI_CTR",	0xFFFFFFFF,	0x00000000},
-        {786,	"MI_AP",	0x00000000,	0x00000000},
-        {787,	"MI_EPN",	0x00000000,	0x00000000},
-        {789,	"MI_TWC",	0xFFFFFE02,	0x00000000},
-        {790,	"MI_RPN",	0x00000000,	0x00000000},
-        {816,	"MI_DBCAM",	0x00000000,	0x00000000},
-        {817,	"MI_DBRAM0",	0x00000000,	0x00000000},
-        {818,	"MI_DBRAM1",	0x00000000,	0x00000000},
-        {792,	"MD_CTR",	0xFFFFFFFF,	0x04000000},
-        {793,	"M_CASID",	0xFFFFFFF0,	0x00000000},
-        {794,	"MD_AP",	0x00000000,	0x00000000},
-        {795,	"MD_EPN",	0x00000000,	0x00000000},
-        {796,	"M_TWB",	0x00000003,	0x00000000},
-        {797,	"MD_TWC",	0x00000003,	0x00000000},
-        {798,	"MD_RPN",	0x00000000,	0x00000000},
-        {799,	"M_TW",		0x00000000,	0x00000000},
-        {824,	"MD_DBCAM",	0x00000000,	0x00000000},
-        {825,	"MD_DBRAM0",	0x00000000,	0x00000000},
-        {826,	"MD_DBRAM1",	0x00000000,	0x00000000},
+	{144,	"CMPA",		0x00000000,	0x00000000},
+	{145,	"CMPB",		0x00000000,	0x00000000},
+	{146,	"CMPC",		0x00000000,	0x00000000},
+	{147,	"CMPD",		0x00000000,	0x00000000},
+	{148,	"ICR",		0xFFFFFFFF,	0x00000000},
+	{149,	"DER",		0x00000000,	0x00000000},
+	{150,	"COUNTA",	0xFFFFFFFF,	0x00000000},
+	{151,	"COUNTB",	0xFFFFFFFF,	0x00000000},
+	{152,	"CMPE",		0x00000000,	0x00000000},
+	{153,	"CMPF",		0x00000000,	0x00000000},
+	{154,	"CMPG",		0x00000000,	0x00000000},
+	{155,	"CMPH",		0x00000000,	0x00000000},
+	{156,	"LCTRL1",	0xFFFFFFFF,	0x00000000},
+	{157,	"LCTRL2",	0xFFFFFFFF,	0x00000000},
+	{158,	"ICTRL",	0xFFFFFFFF,	0x00000007},
+	{159,	"BAR",		0x00000000,	0x00000000},
+	{630,	"DPDR",		0x00000000,	0x00000000},
+	{631,	"DPIR",		0x00000000,	0x00000000},
+	{638,	"IMMR",		0xFFFF0000,	CFG_IMMR  },
+	{560,	"IC_CST",	0x8E380000,	0x00000000},
+	{561,	"IC_ADR",	0x00000000,	0x00000000},
+	{562,	"IC_DAT",	0x00000000,	0x00000000},
+	{568,	"DC_CST",	0xEF380000,	0x00000000},
+	{569,	"DC_ADR",	0x00000000,	0x00000000},
+	{570,	"DC_DAT",	0x00000000,	0x00000000},
+	{784,	"MI_CTR",	0xFFFFFFFF,	0x00000000},
+	{786,	"MI_AP",	0x00000000,	0x00000000},
+	{787,	"MI_EPN",	0x00000000,	0x00000000},
+	{789,	"MI_TWC",	0xFFFFFE02,	0x00000000},
+	{790,	"MI_RPN",	0x00000000,	0x00000000},
+	{816,	"MI_DBCAM",	0x00000000,	0x00000000},
+	{817,	"MI_DBRAM0",	0x00000000,	0x00000000},
+	{818,	"MI_DBRAM1",	0x00000000,	0x00000000},
+	{792,	"MD_CTR",	0xFFFFFFFF,	0x04000000},
+	{793,	"M_CASID",	0xFFFFFFF0,	0x00000000},
+	{794,	"MD_AP",	0x00000000,	0x00000000},
+	{795,	"MD_EPN",	0x00000000,	0x00000000},
+	{796,	"M_TWB",	0x00000003,	0x00000000},
+	{797,	"MD_TWC",	0x00000003,	0x00000000},
+	{798,	"MD_RPN",	0x00000000,	0x00000000},
+	{799,	"M_TW",		0x00000000,	0x00000000},
+	{824,	"MD_DBCAM",	0x00000000,	0x00000000},
+	{825,	"MD_DBRAM0",	0x00000000,	0x00000000},
+	{826,	"MD_DBRAM1",	0x00000000,	0x00000000},
 };
 
 static int spr_test_list_size =