X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=src%2Fcc65%2Fcoptc02.c;h=4ba8a30323ae7f70ff2994d3e16d0ff9aa4a9449;hb=f7dfcbcc3daf8426770842b5e6ed3634e0d50c82;hp=816f92c52e95f6c44f080ff248eb86efbafe57f3;hpb=f38852df82b804f021c9a311a324fc3b0b74dbe7;p=cc65

diff --git a/src/cc65/coptc02.c b/src/cc65/coptc02.c
index 816f92c52..4ba8a3032 100644
--- a/src/cc65/coptc02.c
+++ b/src/cc65/coptc02.c
@@ -201,11 +201,14 @@ unsigned Opt65C02Stores (CodeSeg* S)
       	/* Get next entry */
        	CodeEntry* E = CS_GetEntry (S, I);
 
-	/* Check for the sequence */
-	if (E->OPC == OP65_STA      	       	        &&
+	/* Check for a store with a register value of zero and an addressing
+	 * mode available with STZ.
+	 */
+       	if (((E->OPC == OP65_STA && E->RI->In.RegA == 0) ||
+	     (E->OPC == OP65_STX && E->RI->In.RegX == 0) ||
+	     (E->OPC == OP65_STY && E->RI->In.RegY == 0))     	&&
             (E->AM == AM65_ZP  || E->AM == AM65_ABS ||
-             E->AM == AM65_ZPX || E->AM == AM65_ABSX )  &&
-            E->RI->In.RegA == 0) {
+             E->AM == AM65_ZPX || E->AM == AM65_ABSX)) {
 
             /* Replace by STZ */
             CodeEntry* X = NewCodeEntry (OP65_STZ, E->AM, E->Arg, 0, E->LI);