X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=src%2Fcc65%2Fopcodes.h;h=89a7c4117ee417dd30f05f69c32c716ee8fe9436;hb=9fc71c5e93f7e8270dd6f8fc3810b7b731bf1259;hp=1c9684b570c6c09915f43c0f7b543a8d9b8d75af;hpb=369f59c1bb85df1711493229f5c9dddd05a26c51;p=cc65

diff --git a/src/cc65/opcodes.h b/src/cc65/opcodes.h
index 1c9684b57..89a7c4117 100644
--- a/src/cc65/opcodes.h
+++ b/src/cc65/opcodes.h
@@ -6,7 +6,7 @@
 /*                                                                           */
 /*                                                                           */
 /*                                                                           */
-/* (C) 2001      Ullrich von Bassewitz                                       */
+/* (C) 2001-2002 Ullrich von Bassewitz                                       */
 /*               Wacholderweg 14                                             */
 /*               D-70597 Stuttgart                                           */
 /* EMail:        uz@cc65.org                                                 */
@@ -118,6 +118,7 @@ typedef enum {
     OP65_STA,
     OP65_STX,
     OP65_STY,
+    OP65_STZ,
     OP65_TAX,
     OP65_TAY,
     OP65_TRB,
@@ -126,17 +127,33 @@ typedef enum {
     OP65_TXA,
     OP65_TXS,
     OP65_TYA,
-    OPCODE_COUNT       	       	/* Number of opcodes available */
+
+    /* Number of opcodes available */
+    OPCODE_COUNT,
+
+    /* Several other opcode information constants */
+    OP65_FIRST = OP65_ADC,
+    OP65_LAST  = OP65_TYA,
+    OP65_COUNT = OP65_LAST - OP65_FIRST + 1
 } opc_t;
 
-/* Addressing modes (bitmapped). */
+/* Addressing modes */
 typedef enum {
-    AM65_IMP,      	   	/* implicit */
-    AM65_ACC,      	   	/* accumulator */
-    AM65_IMM,      	   	/* immidiate */
-    AM65_ZP,       	   	/* zeropage */
-    AM65_ZPX,      	   	/* zeropage,X */
-    AM65_ABS,      	   	/* absolute */
+
+    /* Addressing modes of the virtual stack machine */
+    AM_IMP,
+    AM_IMM,
+    AM_STACK,
+    AM_ABS,
+
+    /* 65XX addressing modes */
+    AM65_IMP,       	   	/* implicit */
+    AM65_ACC,       	   	/* accumulator */
+    AM65_IMM,       	   	/* immidiate */
+    AM65_ZP,        	   	/* zeropage */
+    AM65_ZPX,       	   	/* zeropage,X */
+    AM65_ZPY,                   /* zeropage,Y */
+    AM65_ABS,       	   	/* absolute */
     AM65_ABSX,      	   	/* absolute,X */
     AM65_ABSY,      	   	/* absolute,Y */
     AM65_ZPX_IND,      		/* (zeropage,x) */
@@ -149,7 +166,7 @@ typedef enum {
 typedef enum {
     BC_CC,
     BC_CS,
-    BC_EQ,		   
+    BC_EQ,
     BC_MI,
     BC_NE,
     BC_PL,
@@ -158,16 +175,20 @@ typedef enum {
 } bc_t;
 
 /* Opcode info */
-#define OF_NONE	0x0000U	       	    	/* No additional information */
-#define OF_UBRA	0x0001U	       	    	/* Unconditional branch */
-#define OF_CBRA	0x0002U	       	    	/* Conditional branch */
-#define OF_ZBRA 0x0004U	   	    	/* Branch on zero flag condition */
-#define OF_FBRA 0x0008U                 /* Branch on cond set by a load */
-#define OF_LBRA 0x0010U	   	    	/* Jump/branch is long */
-#define OF_RET 	0x0020U	       	    	/* Return from function */
-#define OF_LOAD 0x0040U	   	    	/* Register load */
-#define OF_XFR  0x0080U                 /* Transfer instruction */
-#define OF_CALL 0x0100U                 /* A subroutine call */
+#define OF_NONE	        0x0000U	/* No additional information */
+#define OF_UBRA	        0x0001U	/* Unconditional branch */
+#define OF_CBRA	        0x0002U	/* Conditional branch */
+#define OF_ZBRA         0x0004U	/* Branch on zero flag condition */
+#define OF_FBRA         0x0008U /* Branch on cond set by a load */
+#define OF_LBRA         0x0010U	/* Jump/branch is long */
+#define OF_RET 	        0x0020U	/* Return from function */
+#define OF_LOAD         0x0040U	/* Register load */
+#define OF_STORE        0x0080U /* Register store */
+#define OF_XFR          0x0100U /* Transfer instruction */
+#define OF_CALL         0x0200U /* A subroutine call */
+#define OF_REG_INCDEC   0x0400U /* A register increment or decrement */
+#define OF_SETF         0x0800U /* Insn will set all load flags (not carry) */
+#define OF_CMP          0x1000U /* A compare A/X/Y instruction */
 
 /* Combined infos */
 #define OF_BRA 	(OF_UBRA | OF_CBRA)	/* Operation is a jump/branch */
@@ -176,10 +197,10 @@ typedef enum {
 /* Opcode description */
 typedef struct {
     opc_t      	    OPC;       		/* Opcode */
-    char       	    Mnemo[8];  		/* Mnemonic */
+    char       	    Mnemo[9];  		/* Mnemonic */
     unsigned char   Size;      		/* Size, 0 = check addressing mode */
-    unsigned char   Use;       		/* Registers used by this insn */
-    unsigned char   Chg;       		/* Registers changed by this insn */
+    unsigned short  Use;       		/* Registers used by this insn */
+    unsigned short  Chg;       		/* Registers changed by this insn */
     unsigned short  Info;      		/* Additional information */
 } OPCDesc;
 
@@ -194,7 +215,7 @@ extern const OPCDesc OPCTable[OPCODE_COUNT];
 
 
 
-const OPCDesc* FindOpcode (const char* OPC);
+const OPCDesc* FindOP65 (const char* OPC);
 /* Find the given opcode and return the opcode description. If the opcode was
  * not found, NULL is returned.
  */