X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=src%2Fflash%2Fnor%2Fat91sam4.c;h=4d5ba2e074dc315fd736d79704f5cb43f746f10c;hb=b1a1a48b30243d3582a8443f4baf3dd500683eda;hp=2615c3d750b243fe895b6e635a7255ce71db5b59;hpb=a58f294ac49c0b499e9eb427f81fe85a6e7a4338;p=openocd

diff --git a/src/flash/nor/at91sam4.c b/src/flash/nor/at91sam4.c
index 2615c3d7..4d5ba2e0 100644
--- a/src/flash/nor/at91sam4.c
+++ b/src/flash/nor/at91sam4.c
@@ -504,6 +504,41 @@ static const struct sam4_chip_details all_sam4_details[] = {
 		},
 	},
 
+	/* at91samg53n19 */
+	{
+		.chipid_cidr    = 0x247e0ae0,
+		.name           = "at91samg53n19",
+		.total_flash_size     = 512 * 1024,
+		.total_sram_size      = 96 * 1024,
+		.n_gpnvms       = 2,
+		.n_banks        = 1,
+
+/*		.bank[0] = {*/
+		{
+			{
+				.probed = 0,
+				.pChip  = NULL,
+				.pBank  = NULL,
+				.bank_number = 0,
+				.base_address = FLASH_BANK_BASE_S,
+				.controller_address = 0x400e0a00,
+				.flash_wait_states = 6,	/* workaround silicon bug */
+				.present = 1,
+				.size_bytes =  512 * 1024,
+				.nsectors   =  64,
+				.sector_size = 8192,
+				.page_size   = 512,
+			},
+/*		.bank[1] = {*/
+		  {
+			.present = 0,
+			.probed = 0,
+			.bank_number = 1,
+
+		  },
+		}
+	},
+
 	/* terminate */
 	{
 		.chipid_cidr    = 0,
@@ -1002,7 +1037,7 @@ static uint32_t sam4_reg_fieldname(struct sam4_chip *pChip,
 	}
 
 	/* show the basics */
-	LOG_USER_N("\t%*s: %*d [0x%0*x] ",
+	LOG_USER_N("\t%*s: %*" PRId32 " [0x%0*" PRIx32 "] ",
 		REG_NAME_WIDTH, regname,
 		dwidth, v,
 		hwidth, v);
@@ -1078,6 +1113,10 @@ static const struct archnames { unsigned value; const char *name; } archnames[]
 	{ 0x3B,  "CAP11 Series"                                                         },
 	{ 0x40,  "AT91x40 Series"                                                       },
 	{ 0x42,  "AT91x42 Series"                                                       },
+	{ 0x43,  "SAMG51 Series"
+	},
+	{ 0x47,  "SAMG53 Series"
+	},
 	{ 0x55,  "AT91x55 Series"                                                       },
 	{ 0x60,  "AT91SAM7Axx Series"                                           },
 	{ 0x61,  "AT91SAM7AQxx Series"                                          },
@@ -1227,10 +1266,10 @@ static void sam4_explain_ckgr_mcfr(struct sam4_chip *pChip)
 	v = (v * pChip->cfg.slow_freq) / 16;
 	pChip->cfg.mainosc_freq = v;
 
-	LOG_USER("(%3.03f Mhz (%d.%03dkhz slowclk)",
+	LOG_USER("(%3.03f Mhz (%" PRIu32 ".%03" PRIu32 "khz slowclk)",
 		_tomhz(v),
-		pChip->cfg.slow_freq / 1000,
-		pChip->cfg.slow_freq % 1000);
+		(uint32_t)(pChip->cfg.slow_freq / 1000),
+		(uint32_t)(pChip->cfg.slow_freq % 1000));
 }
 
 static void sam4_explain_ckgr_plla(struct sam4_chip *pChip)
@@ -1246,8 +1285,8 @@ static void sam4_explain_ckgr_plla(struct sam4_chip *pChip)
 		LOG_USER("\tPLLA Freq: (Disabled,mula = 0)");
 	else if (diva == 0)
 		LOG_USER("\tPLLA Freq: (Disabled,diva = 0)");
-	else if (diva == 1) {
-		pChip->cfg.plla_freq = (pChip->cfg.mainosc_freq * (mula + 1));
+	else if (diva >= 1) {
+		pChip->cfg.plla_freq = (pChip->cfg.mainosc_freq * (mula + 1) / diva);
 		LOG_USER("\tPLLA Freq: %3.03f MHz",
 			_tomhz(pChip->cfg.plla_freq));
 	}
@@ -1398,7 +1437,7 @@ static const struct sam4_reg_list sam4_all_regs[] = {
 
 static struct sam4_bank_private *get_sam4_bank_private(struct flash_bank *bank)
 {
-	return (struct sam4_bank_private *)(bank->driver_priv);
+	return bank->driver_priv;
 }
 
 /**
@@ -1479,7 +1518,7 @@ static int sam4_GetInfo(struct sam4_chip *pChip)
 		/* display all regs */
 		LOG_DEBUG("Start: %s", pReg->name);
 		regval = *sam4_get_reg_ptr(&(pChip->cfg), pReg);
-		LOG_USER("%*s: [0x%08x] -> 0x%08x",
+		LOG_USER("%*s: [0x%08" PRIx32 "] -> 0x%08" PRIx32,
 			REG_NAME_WIDTH,
 			pReg->name,
 			pReg->address,
@@ -1495,7 +1534,7 @@ static int sam4_GetInfo(struct sam4_chip *pChip)
 	LOG_USER(" cpu-freq: %3.03f MHz", _tomhz(pChip->cfg.cpu_freq));
 	LOG_USER("mclk-freq: %3.03f MHz", _tomhz(pChip->cfg.mclk_freq));
 
-	LOG_USER(" UniqueId: 0x%08x 0x%08x 0x%08x 0x%08x",
+	LOG_USER(" UniqueId: 0x%08" PRIx32 " 0x%08" PRIx32 " 0x%08" PRIx32 " 0x%08"PRIx32,
 		pChip->cfg.unique_id[0],
 		pChip->cfg.unique_id[1],
 		pChip->cfg.unique_id[2],
@@ -1619,7 +1658,7 @@ static int sam4_GetDetails(struct sam4_bank_private *pPrivate)
 		LOG_ERROR("SAM4 ChipID 0x%08x not found in table (perhaps you can ID this chip?)",
 			(unsigned int)(pPrivate->pChip->cfg.CHIPID_CIDR));
 		/* Help the victim, print details about the chip */
-		LOG_INFO("SAM4 CHIPID_CIDR: 0x%08x decodes as follows",
+		LOG_INFO("SAM4 CHIPID_CIDR: 0x%08" PRIx32 " decodes as follows",
 			pPrivate->pChip->cfg.CHIPID_CIDR);
 		sam4_explain_chipid_cidr(pPrivate->pChip);
 		return ERROR_FAIL;
@@ -1838,7 +1877,7 @@ static int sam4_page_read(struct sam4_bank_private *pPrivate, unsigned pagenum,
 	return r;
 }
 
-static int sam4_page_write(struct sam4_bank_private *pPrivate, unsigned pagenum, uint8_t *buf)
+static int sam4_page_write(struct sam4_bank_private *pPrivate, unsigned pagenum, const uint8_t *buf)
 {
 	uint32_t adr;
 	uint32_t status;
@@ -1900,7 +1939,7 @@ static int sam4_page_write(struct sam4_bank_private *pPrivate, unsigned pagenum,
 }
 
 static int sam4_write(struct flash_bank *bank,
-	uint8_t *buffer,
+	const uint8_t *buffer,
 	uint32_t offset,
 	uint32_t count)
 {