X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=src%2Fflash%2Fnor%2Fnrf51.c;h=334f95f280c11a2f1af2e2a164b42f50ab85c29a;hb=6581bf5f15f404a9a219cfed8eebced76b4414a5;hp=65ad33de27b0c30d537c1e6c8c3a23a092c0c2c7;hpb=e673689df3b6b04074b6f30ce54f5c775b59ae7f;p=openocd

diff --git a/src/flash/nor/nrf51.c b/src/flash/nor/nrf51.c
index 65ad33de..334f95f2 100644
--- a/src/flash/nor/nrf51.c
+++ b/src/flash/nor/nrf51.c
@@ -192,6 +192,18 @@ static const struct nrf51_device_spec nrf51_known_devices_table[] = {
 		.build_code	= "G0",
 		.flash_size_kb	= 256,
 	},
+	{
+		.hwid		= 0x0057,
+		.variant	= "QFAA",
+		.build_code	= "G2",
+		.flash_size_kb	= 256,
+	},
+	{
+		.hwid		= 0x0058,
+		.variant	= "QFAA",
+		.build_code	= "G3",
+		.flash_size_kb	= 256,
+	},
 	{
 		.hwid		= 0x004C,
 		.variant	= "QFAB",
@@ -236,6 +248,12 @@ static const struct nrf51_device_spec nrf51_known_devices_table[] = {
 		.build_code	= "A0",
 		.flash_size_kb	= 256,
 	},
+	{
+		.hwid		= 0x0084,
+		.variant	= "QFAC",
+		.build_code	= "A1",
+		.flash_size_kb	= 256,
+	},
 	{
 		.hwid		= 0x007D,
 		.variant	= "CDAB",
@@ -314,12 +332,6 @@ static const struct nrf51_device_spec nrf51_known_devices_table[] = {
 		.build_code	= "B0",
 		.flash_size_kb	= 128,
 	},
-	{
-		.hwid		= 0x0084,
-		.variant	= "QFAC",
-		.build_code	= "A1",
-		.flash_size_kb	= 256,
-	},
 	{
 		.hwid		= 0x0085,
 		.variant	= "QFAC",
@@ -351,15 +363,6 @@ static const struct nrf51_device_spec nrf51_known_devices_table[] = {
 		.flash_size_kb	= 256,
 	},
 
-	/* mdbt40
-	   no idea if variant and build code are correct */
-	{
-		.hwid		= 0x0057,
-		.variant	= "QFAA",
-		.build_code	= "G2",
-		.flash_size_kb	= 256,
-	},
-
 	/* Some early nRF51-DK (PCA10028) & nRF51-Dongle (PCA10031) boards
 	   with built-in jlink seem to use engineering samples not listed
 	   in the nRF51 Series Compatibility Matrix V1.0. */
@@ -584,7 +587,7 @@ static int nrf51_protect(struct flash_bank *bank, int set, int first, int last)
 	if ((ppfc & 0xFF) == 0x00) {
 		LOG_ERROR("Code region 0 size was pre-programmed at the factory, can't change flash protection settings");
 		return ERROR_FAIL;
-	};
+	}
 
 	res = target_read_u32(chip->target, NRF51_UICR_CLENR0,
 			      &clenr0);
@@ -764,7 +767,7 @@ static int nrf51_erase_page(struct flash_bank *bank,
 
 			LOG_ERROR("The chip was not pre-programmed with SoftDevice stack and UICR cannot be erased separately. Please issue mass erase before trying to write to this region");
 			return ERROR_FAIL;
-		};
+		}
 
 		res = nrf51_nvmc_generic_erase(chip,
 					       NRF51_NVMC_ERASEUICR,
@@ -1145,7 +1148,7 @@ COMMAND_HANDLER(nrf51_handle_mass_erase_command)
 		LOG_ERROR("Code region 0 size was pre-programmed at the factory, "
 			  "mass erase command won't work.");
 		return ERROR_FAIL;
-	};
+	}
 
 	res = nrf51_erase_all(chip);
 	if (res != ERROR_OK) {