X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=src%2Fflash%2Fs3c2440_nand.c;h=40037c7f262c09da77ed4be81cbaf4fc1bb0a308;hb=6aa82891b60dc4a332ac548c13fc8d207bf171b0;hp=80020f63def9ed1601f1f34f4554cec7834c8b57;hpb=670f999e7a1ec04cda599a5487de068379e36f0e;p=openocd

diff --git a/src/flash/s3c2440_nand.c b/src/flash/s3c2440_nand.c
index 80020f63..40037c7f 100644
--- a/src/flash/s3c2440_nand.c
+++ b/src/flash/s3c2440_nand.c
@@ -33,7 +33,7 @@
 
 NAND_DEVICE_COMMAND_HANDLER(s3c2440_nand_device_command)
 {
-	s3c24xx_nand_controller_t *info;
+	struct s3c24xx_nand_controller *info;
 	CALL_S3C24XX_DEVICE_COMMAND(nand, &info);
 
 	/* fill in the address fields for the core device */
@@ -47,7 +47,7 @@ NAND_DEVICE_COMMAND_HANDLER(s3c2440_nand_device_command)
 
 static int s3c2440_init(struct nand_device_s *nand)
 {
-	s3c24xx_nand_controller_t *s3c24xx_info = nand->controller_priv;
+	struct s3c24xx_nand_controller *s3c24xx_info = nand->controller_priv;
 	target_t *target = s3c24xx_info->target;
 
 	target_write_u32(target, S3C2410_NFCONF,
@@ -63,7 +63,7 @@ static int s3c2440_init(struct nand_device_s *nand)
 
 int s3c2440_nand_ready(struct nand_device_s *nand, int timeout)
 {
-	s3c24xx_nand_controller_t *s3c24xx_info = nand->controller_priv;
+	struct s3c24xx_nand_controller *s3c24xx_info = nand->controller_priv;
 	target_t *target = s3c24xx_info->target;
 	uint8_t status;
 
@@ -89,7 +89,7 @@ int s3c2440_nand_ready(struct nand_device_s *nand, int timeout)
 
 int s3c2440_read_block_data(struct nand_device_s *nand, uint8_t *data, int data_size)
 {
-	s3c24xx_nand_controller_t *s3c24xx_info = nand->controller_priv;
+	struct s3c24xx_nand_controller *s3c24xx_info = nand->controller_priv;
 	target_t *target = s3c24xx_info->target;
 	uint32_t nfdata = s3c24xx_info->data;
 	uint32_t tmp;
@@ -125,7 +125,7 @@ int s3c2440_read_block_data(struct nand_device_s *nand, uint8_t *data, int data_
 
 int s3c2440_write_block_data(struct nand_device_s *nand, uint8_t *data, int data_size)
 {
-	s3c24xx_nand_controller_t *s3c24xx_info = nand->controller_priv;
+	struct s3c24xx_nand_controller *s3c24xx_info = nand->controller_priv;
 	target_t *target = s3c24xx_info->target;
 	uint32_t nfdata = s3c24xx_info->data;
 	uint32_t tmp;
@@ -153,7 +153,7 @@ int s3c2440_write_block_data(struct nand_device_s *nand, uint8_t *data, int data
 	return ERROR_OK;
 }
 
-nand_flash_controller_t s3c2440_nand_controller = {
+struct nand_flash_controller s3c2440_nand_controller = {
 		.name = "s3c2440",
 		.nand_device_command = &s3c2440_nand_device_command,
 		.register_commands = &s3c24xx_register_commands,