X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=src%2Fflash%2Fs3c2440_nand.c;h=40037c7f262c09da77ed4be81cbaf4fc1bb0a308;hb=6aa82891b60dc4a332ac548c13fc8d207bf171b0;hp=fd1fbd0acdff5999c168e82c87b94bf1ea36b498;hpb=e8e94ab2454566fb9a226693e5c1de2264634a48;p=openocd

diff --git a/src/flash/s3c2440_nand.c b/src/flash/s3c2440_nand.c
index fd1fbd0a..40037c7f 100644
--- a/src/flash/s3c2440_nand.c
+++ b/src/flash/s3c2440_nand.c
@@ -31,16 +31,10 @@
 #include "s3c24xx_nand.h"
 
 
-static int s3c2440_nand_device_command(struct command_context_s *cmd_ctx, char *cmd,
-				char **args, int argc,
-				struct nand_device_s *nand)
+NAND_DEVICE_COMMAND_HANDLER(s3c2440_nand_device_command)
 {
-	s3c24xx_nand_controller_t *info;
-
-	info = s3c24xx_nand_device_command(cmd_ctx, cmd, args, argc, nand);
-	if (info == NULL) {
-		return ERROR_NAND_DEVICE_INVALID;
-	}
+	struct s3c24xx_nand_controller *info;
+	CALL_S3C24XX_DEVICE_COMMAND(nand, &info);
 
 	/* fill in the address fields for the core device */
 	info->cmd = S3C2440_NFCMD;
@@ -53,7 +47,7 @@ static int s3c2440_nand_device_command(struct command_context_s *cmd_ctx, char *
 
 static int s3c2440_init(struct nand_device_s *nand)
 {
-	s3c24xx_nand_controller_t *s3c24xx_info = nand->controller_priv;
+	struct s3c24xx_nand_controller *s3c24xx_info = nand->controller_priv;
 	target_t *target = s3c24xx_info->target;
 
 	target_write_u32(target, S3C2410_NFCONF,
@@ -69,7 +63,7 @@ static int s3c2440_init(struct nand_device_s *nand)
 
 int s3c2440_nand_ready(struct nand_device_s *nand, int timeout)
 {
-	s3c24xx_nand_controller_t *s3c24xx_info = nand->controller_priv;
+	struct s3c24xx_nand_controller *s3c24xx_info = nand->controller_priv;
 	target_t *target = s3c24xx_info->target;
 	uint8_t status;
 
@@ -95,7 +89,7 @@ int s3c2440_nand_ready(struct nand_device_s *nand, int timeout)
 
 int s3c2440_read_block_data(struct nand_device_s *nand, uint8_t *data, int data_size)
 {
-	s3c24xx_nand_controller_t *s3c24xx_info = nand->controller_priv;
+	struct s3c24xx_nand_controller *s3c24xx_info = nand->controller_priv;
 	target_t *target = s3c24xx_info->target;
 	uint32_t nfdata = s3c24xx_info->data;
 	uint32_t tmp;
@@ -131,7 +125,7 @@ int s3c2440_read_block_data(struct nand_device_s *nand, uint8_t *data, int data_
 
 int s3c2440_write_block_data(struct nand_device_s *nand, uint8_t *data, int data_size)
 {
-	s3c24xx_nand_controller_t *s3c24xx_info = nand->controller_priv;
+	struct s3c24xx_nand_controller *s3c24xx_info = nand->controller_priv;
 	target_t *target = s3c24xx_info->target;
 	uint32_t nfdata = s3c24xx_info->data;
 	uint32_t tmp;
@@ -159,7 +153,7 @@ int s3c2440_write_block_data(struct nand_device_s *nand, uint8_t *data, int data
 	return ERROR_OK;
 }
 
-nand_flash_controller_t s3c2440_nand_controller = {
+struct nand_flash_controller s3c2440_nand_controller = {
 		.name = "s3c2440",
 		.nand_device_command = &s3c2440_nand_device_command,
 		.register_commands = &s3c24xx_register_commands,