X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=src%2Fflash%2Fs3c24xx_nand.h;h=6cfad3d311f2e6b54fd1a54ce8b2883b63d43eac;hb=40273967bf535aefb3eaec9367c50e7799b079bb;hp=8f96f2d27fb026a4d9b883e780d85a42dc45938f;hpb=0643263d68bcddc56eaa7e3678b7502798410711;p=openocd

diff --git a/src/flash/s3c24xx_nand.h b/src/flash/s3c24xx_nand.h
index 8f96f2d2..6cfad3d3 100644
--- a/src/flash/s3c24xx_nand.h
+++ b/src/flash/s3c24xx_nand.h
@@ -18,6 +18,9 @@
  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  ***************************************************************************/
 
+#ifndef S3C24xx_NAND_H
+#define S3C24xx_NAND_H
+
 /*
  * S3C24XX Series OpenOCD NAND Flash controller support.
  *
@@ -27,37 +30,57 @@
 #include "nand.h"
 #include "s3c24xx_regs_nand.h"
 
-typedef struct s3c24xx_nand_controller_s
+struct s3c24xx_nand_controller
 {
 	struct target_s *target;
-	
+
 	/* register addresses */
-	u32		 cmd;
-	u32		 addr;
-	u32		 data;
-	u32		 nfstat; 
-} s3c24xx_nand_controller_t;
+	uint32_t		 cmd;
+	uint32_t		 addr;
+	uint32_t		 data;
+	uint32_t		 nfstat;
+};
 
 /* Default to using the un-translated NAND register based address */
 #undef S3C2410_NFREG
 #define S3C2410_NFREG(x) ((x) + 0x4e000000)
 
-extern s3c24xx_nand_controller_t *s3c24xx_nand_device_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct nand_device_s *device);
+#define S3C24XX_DEVICE_COMMAND() \
+		COMMAND_HELPER(s3c24xx_nand_device_command, \
+				struct nand_device_s *nand, \
+				struct s3c24xx_nand_controller **info)
+
+S3C24XX_DEVICE_COMMAND();
+
+#define CALL_S3C24XX_DEVICE_COMMAND(d, i) \
+	do { \
+		int retval = CALL_COMMAND_HANDLER(s3c24xx_nand_device_command, d, i); \
+		if (ERROR_OK != retval) \
+			return retval; \
+	} while (0)
+
+int s3c24xx_register_commands(struct command_context_s *cmd_ctx);
 
-extern int s3c24xx_register_commands(struct command_context_s *cmd_ctx);
-extern int s3c24xx_reset(struct nand_device_s *device);
-extern int s3c24xx_command(struct nand_device_s *device, u8 command);
-extern int s3c24xx_address(struct nand_device_s *device, u8 address);
-extern int s3c24xx_write_data(struct nand_device_s *device, u16 data);
-extern int s3c24xx_read_data(struct nand_device_s *device, void *data);
-extern int s3c24xx_controller_ready(struct nand_device_s *device, int tout);
+int s3c24xx_reset(struct nand_device_s *nand);
+
+int s3c24xx_command(struct nand_device_s *nand, uint8_t command);
+int s3c24xx_address(struct nand_device_s *nand, uint8_t address);
+
+int s3c24xx_write_data(struct nand_device_s *nand, uint16_t data);
+int s3c24xx_read_data(struct nand_device_s *nand, void *data);
+
+int s3c24xx_controller_ready(struct nand_device_s *nand, int tout);
 
 #define s3c24xx_write_page NULL
 #define s3c24xx_read_page NULL
 
 /* code shared between different controllers */
 
-extern int s3c2440_nand_ready(struct nand_device_s *device, int timeout);
+int s3c2440_nand_ready(struct nand_device_s *nand, int timeout);
+
+int s3c2440_read_block_data(struct nand_device_s *nand,
+		uint8_t *data, int data_size);
+int s3c2440_write_block_data(struct nand_device_s *nand,
+		uint8_t *data, int data_size);
 
-extern int s3c2440_read_block_data(struct nand_device_s *, u8 *data, int data_size);
-extern int s3c2440_write_block_data(struct nand_device_s *, u8 *data, int data_size);
+#endif // S3C24xx_NAND_H