X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=src%2Fjtag%2Fdrivers%2Famt_jtagaccel.c;h=121649bcb2cc6ffd369da292cb6417b26b53c190;hb=2bc7446bb8caf751f7d6900af26384f6c64cc791;hp=8ba15838462ecb9cf4043168653b14bf9051f57a;hpb=165fb9309d16ff91967f26ce8c01bfd176371506;p=openocd diff --git a/src/jtag/drivers/amt_jtagaccel.c b/src/jtag/drivers/amt_jtagaccel.c index 8ba15838..121649bc 100644 --- a/src/jtag/drivers/amt_jtagaccel.c +++ b/src/jtag/drivers/amt_jtagaccel.c @@ -22,8 +22,6 @@ #endif #include -#include - #if PARPORT_USE_PPDEV == 1 #include @@ -41,6 +39,15 @@ #endif #endif +/** + * @file + * Support the Amontec Chameleon POD with JTAG Accelerator support. + * This is a parallel port JTAG adapter with a CPLD between the + * parallel port and the JTAG connection. VHDL code running in the + * CPLD significantly accelerates JTAG operations compared to the + * bitbanging "Wiggler" style of most parallel port adapters. + */ + /* configuration */ static uint16_t amt_jtagaccel_port; @@ -55,13 +62,41 @@ static int rtck_enabled = 0; #if PARPORT_USE_PPDEV == 1 static int device_handle; -static int addr_mode = IEEE1284_MODE_EPP | IEEE1284_ADDR ; -#define AMT_AW(val) do { ioctl(device_handle, PPSETMODE, &addr_mode); write(device_handle, &val, 1); } while (0) -#define AMT_AR(val) do { ioctl(device_handle, PPSETMODE, &addr_mode); read(device_handle, &val, 1); } while (0) - -static int data_mode = IEEE1284_MODE_EPP | IEEE1284_DATA ; -#define AMT_DW(val) do { ioctl(device_handle, PPSETMODE, &data_mode); write(device_handle, &val, 1); } while (0) -#define AMT_DR(val) do { ioctl(device_handle, PPSETMODE, &data_mode); read(device_handle, &val, 1); } while (0) +static const int addr_mode = IEEE1284_MODE_EPP | IEEE1284_ADDR; + +/* FIXME do something sane when these ioctl/read/write calls fail. */ + +#define AMT_AW(val) \ + do { \ + int __retval; \ + \ + __retval = ioctl(device_handle, PPSETMODE, &addr_mode); \ + __retval = write(device_handle, &val, 1); \ + } while (0) +#define AMT_AR(val) \ + do { \ + int __retval; \ + \ + __retval = ioctl(device_handle, PPSETMODE, &addr_mode); \ + __retval = read(device_handle, &val, 1); \ + } while (0) + +static const int data_mode = IEEE1284_MODE_EPP | IEEE1284_DATA; + +#define AMT_DW(val) \ + do { \ + int __retval; \ + \ + __retval = ioctl(device_handle, PPSETMODE, &data_mode); \ + __retval = write(device_handle, &val, 1); \ + } while (0) +#define AMT_DR(val) \ + do { \ + int __retval; \ + \ + __retval = ioctl(device_handle, PPSETMODE, &data_mode); \ + __retval = read(device_handle, &val, 1); \ + } while (0) #else @@ -545,24 +580,31 @@ static const struct command_registration amtjtagaccel_command_handlers[] = { .name = "parport_port", .handler = &amt_jtagaccel_handle_parport_port_command, .mode = COMMAND_CONFIG, - .help = "configure the parallel port to use", - .usage = "", + .help = "configure or display the parallel port to use", + .usage = "[port_num]", }, { - .name = "parport_port", + /** + * @todo Remove this "rtck" command; just use the standard + * mechanism to enable/disable adaptive clocking. First + * implement the standard mechanism and deprecate "rtck"; + * after a year or so, it'll be safe to remove this. + */ + .name = "rtck", .handler = &amt_jtagaccel_handle_rtck_command, .mode = COMMAND_CONFIG, - .help = "enable RTCK", - .usage = "", + .help = "configure or display RTCK support", + .usage = "[enable|disable]", }, COMMAND_REGISTRATION_DONE }; struct jtag_interface amt_jtagaccel_interface = { - .name = "amt_jtagaccel", - .commands = amtjtagaccel_command_handlers, - .init = &amt_jtagaccel_init, - .quit = &amt_jtagaccel_quit, - .speed = &amt_jtagaccel_speed, - .execute_queue = &amt_jtagaccel_execute_queue, - }; + .name = "amt_jtagaccel", + .commands = amtjtagaccel_command_handlers, + + .init = amt_jtagaccel_init, + .quit = amt_jtagaccel_quit, + .speed = amt_jtagaccel_speed, + .execute_queue = amt_jtagaccel_execute_queue, +};