X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=src%2Ftarget%2Farm11.c;h=0f8faba33132b4f76a46d3411e767a6b06a0f57b;hb=ed8fd94d7ca0fc0682de4020501afae89f31ccc3;hp=7cb24dfb982573bb3ccd354c92264a5f44d1a391;hpb=d84bba66ae1cf395c4f0229b6708b7fd5f1bdad9;p=openocd diff --git a/src/target/arm11.c b/src/target/arm11.c index 7cb24dfb..0f8faba3 100644 --- a/src/target/arm11.c +++ b/src/target/arm11.c @@ -2,7 +2,7 @@ * Copyright (C) 2008 digenius technology GmbH. * * Michael Bruck * * * - * Copyright (C) 2008 Oyvind Harboe oyvind.harboe@zylin.com * + * Copyright (C) 2008,2009 Oyvind Harboe oyvind.harboe@zylin.com * * * * Copyright (C) 2008 Georg Acher * * * @@ -27,6 +27,8 @@ #endif #include "arm11.h" +#include "armv4_5.h" +#include "arm_simulator.h" #include "target_type.h" @@ -53,6 +55,7 @@ bool arm11_config_memwrite_error_fatal = true; uint32_t arm11_vcr = 0; bool arm11_config_memrw_no_increment = false; bool arm11_config_step_irq_enable = false; +bool arm11_config_hardware_step = false; #define ARM11_HANDLER(x) \ .x = arm11_##x @@ -371,6 +374,7 @@ int arm11_check_init(arm11_common_t * arm11, uint32_t * dscr) */ static int arm11_on_enter_debug_state(arm11_common_t * arm11) { + int retval; FNC_INFO; for (size_t i = 0; i < asizeof(arm11->reg_values); i++) @@ -456,7 +460,9 @@ static int arm11_on_enter_debug_state(arm11_common_t * arm11) for (size_t i = 0; i < 15; i++) { /* MCR p14,0,R?,c0,c5,0 */ - arm11_run_instr_data_from_core(arm11, 0xEE000E15 | (i << 12), &R(RX + i), 1); + retval = arm11_run_instr_data_from_core(arm11, 0xEE000E15 | (i << 12), &R(RX + i), 1); + if (retval != ERROR_OK) + return retval; } /* save rDTR */ @@ -481,7 +487,9 @@ static int arm11_on_enter_debug_state(arm11_common_t * arm11) /* save PC */ /* MOV R0,PC (move PC -> r0 (-> wDTR -> local var)) */ - arm11_run_instr_data_from_core_via_r0(arm11, 0xE1A0000F, &R(PC)); + retval = arm11_run_instr_data_from_core_via_r0(arm11, 0xE1A0000F, &R(PC)); + if (retval != ERROR_OK) + return retval; /* adjust PC depending on ARM state */ @@ -662,6 +670,7 @@ void arm11_record_register_history(arm11_common_t * arm11) int arm11_poll(struct target_s *target) { FNC_INFO; + int retval; arm11_common_t * arm11 = target->arch_info; @@ -685,7 +694,9 @@ int arm11_poll(struct target_s *target) LOG_DEBUG("enter TARGET_HALTED"); target->state = TARGET_HALTED; target->debug_reason = arm11_get_DSCR_debug_reason(dscr); - arm11_on_enter_debug_state(arm11); + retval = arm11_on_enter_debug_state(arm11); + if (retval != ERROR_OK) + return retval; target_call_event_callbacks(target, old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED); @@ -709,7 +720,7 @@ int arm11_arch_state(struct target_s *target) arm11_common_t * arm11 = target->arch_info; LOG_USER("target halted due to %s\ncpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "", - Jim_Nvp_value2name_simple( nvp_target_debug_reason, target->debug_reason )->name, + Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name, R(CPSR), R(PC)); @@ -732,7 +743,7 @@ int arm11_halt(struct target_s *target) arm11_common_t * arm11 = target->arch_info; LOG_DEBUG("target->state: %s", - Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name ); + target_state_name(target)); if (target->state == TARGET_UNKNOWN) { @@ -789,7 +800,7 @@ int arm11_resume(struct target_s *target, int current, uint32_t address, int han arm11_common_t * arm11 = target->arch_info; LOG_DEBUG("target->state: %s", - Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name ); + target_state_name(target)); if (target->state != TARGET_HALTED) @@ -884,12 +895,99 @@ int arm11_resume(struct target_s *target, int current, uint32_t address, int han return ERROR_OK; } + +static int armv4_5_to_arm11(int reg) +{ + if (reg < 16) + return reg; + switch (reg) + { + case ARMV4_5_CPSR: + return ARM11_RC_CPSR; + case 16: + /* FIX!!! handle thumb better! */ + return ARM11_RC_CPSR; + default: + LOG_ERROR("BUG: register translation from armv4_5 to arm11 not supported %d", reg); + exit(-1); + } +} + + +static uint32_t arm11_sim_get_reg(struct arm_sim_interface *sim, int reg) +{ + arm11_common_t * arm11 = (arm11_common_t *)sim->user_data; + + reg=armv4_5_to_arm11(reg); + + return buf_get_u32(arm11->reg_list[reg].value, 0, 32); +} + +static void arm11_sim_set_reg(struct arm_sim_interface *sim, int reg, uint32_t value) +{ + arm11_common_t * arm11 = (arm11_common_t *)sim->user_data; + + reg=armv4_5_to_arm11(reg); + + buf_set_u32(arm11->reg_list[reg].value, 0, 32, value); +} + +static uint32_t arm11_sim_get_cpsr(struct arm_sim_interface *sim, int pos, int bits) +{ + arm11_common_t * arm11 = (arm11_common_t *)sim->user_data; + + return buf_get_u32(arm11->reg_list[ARM11_RC_CPSR].value, pos, bits); +} + +static enum armv4_5_state arm11_sim_get_state(struct arm_sim_interface *sim) +{ +// arm11_common_t * arm11 = (arm11_common_t *)sim->user_data; + + /* FIX!!!! we should implement thumb for arm11 */ + return ARMV4_5_STATE_ARM; +} + +static void arm11_sim_set_state(struct arm_sim_interface *sim, enum armv4_5_state mode) +{ +// arm11_common_t * arm11 = (arm11_common_t *)sim->user_data; + + /* FIX!!!! we should implement thumb for arm11 */ + LOG_ERROR("Not implemetned!"); +} + + +static enum armv4_5_mode arm11_sim_get_mode(struct arm_sim_interface *sim) +{ + //arm11_common_t * arm11 = (arm11_common_t *)sim->user_data; + + /* FIX!!!! we should implement something that returns the current mode here!!! */ + return ARMV4_5_MODE_USR; +} + +static int arm11_simulate_step(target_t *target, uint32_t *dry_run_pc) +{ + struct arm_sim_interface sim; + + sim.user_data=target->arch_info; + sim.get_reg=&arm11_sim_get_reg; + sim.set_reg=&arm11_sim_set_reg; + sim.get_reg_mode=&arm11_sim_get_reg; + sim.set_reg_mode=&arm11_sim_set_reg; + sim.get_cpsr=&arm11_sim_get_cpsr; + sim.get_mode=&arm11_sim_get_mode; + sim.get_state=&arm11_sim_get_state; + sim.set_state=&arm11_sim_set_state; + + return arm_simulate_step_core(target, dry_run_pc, &sim); + +} + int arm11_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints) { FNC_INFO; LOG_DEBUG("target->state: %s", - Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name ); + target_state_name(target)); if (target->state != TARGET_HALTED) { @@ -904,6 +1002,7 @@ int arm11_step(struct target_s *target, int current, uint32_t address, int handl LOG_DEBUG("STEP PC %08" PRIx32 "%s", R(PC), !current ? "!" : ""); + /** \todo TODO: Thumb not supported here */ uint32_t next_instruction; @@ -947,10 +1046,30 @@ int arm11_step(struct target_s *target, int current, uint32_t address, int handl brp[0].write = 1; brp[0].address = ARM11_SC7_BVR0; - brp[0].value = R(PC); brp[1].write = 1; brp[1].address = ARM11_SC7_BCR0; - brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (2 << 21); + + if (arm11_config_hardware_step) + { + /* hardware single stepping be used if possible or is it better to + * always use the same code path? Hardware single stepping is not supported + * on all hardware + */ + brp[0].value = R(PC); + brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (2 << 21); + } else + { + /* sets a breakpoint on the next PC(calculated by simulation), + */ + uint32_t next_pc; + int retval; + retval = arm11_simulate_step(target, &next_pc); + if (retval != ERROR_OK) + return retval; + + brp[0].value = next_pc; + brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21); + } CHECK_RETVAL(arm11_sc7_run(arm11, brp, asizeof(brp))); @@ -1035,7 +1154,7 @@ int arm11_deassert_reset(struct target_s *target) #if 0 LOG_DEBUG("target->state: %s", - Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name ); + target_state_name(target)); /* deassert reset lines */ @@ -1149,7 +1268,7 @@ int arm11_read_memory(struct target_s *target, uint32_t address, uint32_t size, arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1); uint16_t svalue = res; - memcpy(buffer + count * sizeof(uint16_t), &svalue, sizeof(uint16_t)); + memcpy(buffer + i * sizeof(uint16_t), &svalue, sizeof(uint16_t)); } break; @@ -1219,7 +1338,7 @@ int arm11_write_memory(struct target_s *target, uint32_t address, uint32_t size, for (size_t i = 0; i < count; i++) { uint16_t value; - memcpy(&value, buffer + count * sizeof(uint16_t), sizeof(uint16_t)); + memcpy(&value, buffer + i * sizeof(uint16_t), sizeof(uint16_t)); /* MRC p14,0,r1,c0,c5,0 */ arm11_run_instr_data_to_core1(arm11, 0xee101e15, value); @@ -1399,7 +1518,7 @@ int arm11_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t LOG_DEBUG("Save %zi: 0x%" PRIx32 "",i,context[i]); } - cpsr = buf_get_u32((uint8_t*)(arm11->reg_values+ARM11_RC_CPSR),0,32); + cpsr = buf_get_u32((uint8_t*)(arm11->reg_values + ARM11_RC_CPSR),0,32); LOG_DEBUG("Save CPSR: 0x%" PRIx32 "", cpsr); for (int i = 0; i < num_mem_params; i++) @@ -1540,7 +1659,7 @@ int arm11_target_create(struct target_s *target, Jim_Interp *interp) arm11->target = target; - if (target->tap==NULL) + if (target->tap == NULL) return ERROR_FAIL; if (target->tap->ir_length != 5) @@ -1803,6 +1922,7 @@ BOOL_WRAPPER(memwrite_burst, "memory write burst mode") BOOL_WRAPPER(memwrite_error_fatal, "fatal error mode for memory writes") BOOL_WRAPPER(memrw_no_increment, "\"no increment\" mode for memory transfers") BOOL_WRAPPER(step_irq_enable, "IRQs while stepping") +BOOL_WRAPPER(hardware_step, "hardware single step") int arm11_handle_vcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) { @@ -1888,7 +2008,7 @@ int arm11_handle_mrc_mcr(struct command_context_s *cmd_ctx, char *cmd, char **ar if (values[i] > arm11_coproc_instruction_limits[i]) { LOG_ERROR("Parameter %ld out of bounds (%" PRId32 " max). %s", - (long)(i + 2), + (long)(i + 2), arm11_coproc_instruction_limits[i], read ? arm11_mrc_syntax : arm11_mcr_syntax); return -1; @@ -1913,10 +2033,10 @@ int arm11_handle_mrc_mcr(struct command_context_s *cmd_ctx, char *cmd, char **ar arm11_run_instr_data_from_core_via_r0(arm11, instr, &result); LOG_INFO("MRC p%d, %d, R0, c%d, c%d, %d = 0x%08" PRIx32 " (%" PRId32 ")", - (int)(values[0]), - (int)(values[1]), - (int)(values[2]), - (int)(values[3]), + (int)(values[0]), + (int)(values[1]), + (int)(values[2]), + (int)(values[3]), (int)(values[4]), result, result); } else @@ -1951,32 +2071,34 @@ int arm11_register_commands(struct command_context_s *cmd_ctx) command_t * top_cmd = NULL; - RC_TOP( "arm11", "arm11 specific commands", + RC_TOP("arm11", "arm11 specific commands", - RC_TOP( "memwrite", "Control memory write transfer mode", + RC_TOP("memwrite", "Control memory write transfer mode", - RC_FINAL_BOOL( "burst", "Enable/Disable non-standard but fast burst mode (default: enabled)", + RC_FINAL_BOOL("burst", "Enable/Disable non-standard but fast burst mode (default: enabled)", memwrite_burst) - RC_FINAL_BOOL( "error_fatal", "Terminate program if transfer error was found (default: enabled)", + RC_FINAL_BOOL("error_fatal", "Terminate program if transfer error was found (default: enabled)", memwrite_error_fatal) - ) /* memwrite */ +) /* memwrite */ - RC_FINAL_BOOL( "no_increment", "Don't increment address on multi-read/-write (default: disabled)", + RC_FINAL_BOOL("no_increment", "Don't increment address on multi-read/-write (default: disabled)", memrw_no_increment) - RC_FINAL_BOOL( "step_irq_enable", "Enable interrupts while stepping (default: disabled)", - step_irq_enable) +RC_FINAL_BOOL("step_irq_enable", "Enable interrupts while stepping (default: disabled)", + step_irq_enable) +RC_FINAL_BOOL("hardware_step", "hardware single stepping. By default use simulate + breakpoint. This command is only here to check if simulate + breakpoint implementation is broken.", + hardware_step) - RC_FINAL( "vcr", "Control (Interrupt) Vector Catch Register", + RC_FINAL("vcr", "Control (Interrupt) Vector Catch Register", arm11_handle_vcr) - RC_FINAL( "mrc", "Read Coprocessor register", + RC_FINAL("mrc", "Read Coprocessor register", arm11_handle_mrc) - RC_FINAL( "mcr", "Write Coprocessor register", + RC_FINAL("mcr", "Write Coprocessor register", arm11_handle_mcr) - ) /* arm11 */ +) /* arm11 */ return ERROR_OK; }