X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=src%2Ftarget%2Farm11.h;h=c3f4e8643bfa6fc6aab38551f869734cd6b484d0;hb=97fbd793b3a4edec490b2b034f7b6fe5261ca03e;hp=0b379294225195ab7eb5727f757dcacf258a0ac8;hpb=fa618cc74deea6741c745b4f80dace2421209a1e;p=openocd diff --git a/src/target/arm11.h b/src/target/arm11.h index 0b379294..c3f4e864 100644 --- a/src/target/arm11.h +++ b/src/target/arm11.h @@ -24,34 +24,21 @@ #define ARM11_H #include "armv4_5.h" +#include "arm_dpm.h" -#define NEW(type, variable, items) \ - type * variable = calloc(1, sizeof(type) * items) - -/* TEMPORARY -- till we switch to the shared infrastructure */ -#define ARM11_REGCACHE_COUNT 20 +#define ARM11_REGCACHE_COUNT 3 #define ARM11_TAP_DEFAULT TAP_INVALID - -#define CHECK_RETVAL(action) \ -do { \ - int __retval = (action); \ - \ - if (__retval != ERROR_OK) \ - { \ - LOG_DEBUG("error while calling \"" # action "\""); \ - return __retval; \ - } \ - \ -} while (0) - - -struct arm11_register_history -{ - uint32_t value; - uint8_t valid; -}; +#define CHECK_RETVAL(action) \ + do { \ + int __retval = (action); \ + if (__retval != ERROR_OK) { \ + LOG_DEBUG("error while calling \"%s\"", \ + # action ); \ + return __retval; \ + } \ + } while (0) enum arm11_debug_version { @@ -66,18 +53,15 @@ struct arm11_common struct arm arm; struct target * target; /**< Reference back to the owner */ + /** Debug module state. */ + struct arm_dpm dpm; + /** \name Processor type detection */ /*@{*/ - uint32_t device_id; /**< IDCODE readout */ - uint32_t didr; /**< DIDR readout (debug capabilities) */ - uint8_t implementor; /**< DIDR Implementor readout */ - size_t brp; /**< Number of Breakpoint Register Pairs from DIDR */ size_t wrp; /**< Number of Watchpoint Register Pairs from DIDR */ - enum arm11_debug_version - debug_version; /**< ARM debug architecture from DIDR */ /*@}*/ uint32_t last_dscr; /**< Last retrieved DSCR value; @@ -85,7 +69,7 @@ struct arm11_common bool simulate_reset_on_next_halt; /**< Perform cleanups of the ARM state on next halt */ - /** \name Shadow registers to save processor state */ + /** \name Shadow registers to save debug state */ /*@{*/ struct reg * reg_list; /**< target register list */ @@ -93,9 +77,6 @@ struct arm11_common /*@}*/ - struct arm11_register_history - reg_history[ARM11_REGCACHE_COUNT]; /**< register state before last resume */ - size_t free_brps; /**< keep track of breakpoints allocated by arm11_add_breakpoint() */ size_t free_wrps; /**< keep track of breakpoints allocated by arm11_add_watchpoint() */