X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=src%2Ftarget%2Farm11_dbgtap.c;h=7a639fdee25a3612632532e077cfda170c0c6a78;hb=a229f2143249a0718c010ccb29be02a5eb580fbb;hp=3a50ea072327c49a7476e5b4cd38b228647fb8df;hpb=bd7d019b56a17c133f2696ae0e16f280f01236a8;p=openocd diff --git a/src/target/arm11_dbgtap.c b/src/target/arm11_dbgtap.c index 3a50ea07..7a639fde 100644 --- a/src/target/arm11_dbgtap.c +++ b/src/target/arm11_dbgtap.c @@ -36,6 +36,13 @@ #define JTAG_DEBUG(expr ...) do {} while(0) #endif +/* +This pathmove goes from Pause-IR to Shift-IR while avoiding RTI. The +behavior of the FTDI driver IIRC was to go via RTI. + +Conversely there may be other places in this code where the ARM11 code relies +on the driver to hit through RTI when coming from Update-?R. +*/ tap_state_t arm11_move_pi_to_si_via_ci[] = { TAP_IREXIT2, TAP_IRUPDATE, TAP_DRSELECT, TAP_IRSELECT, TAP_IRCAPTURE, TAP_IRSHIFT @@ -80,7 +87,6 @@ void arm11_setup_field(arm11_common_t * arm11, int num_bits, void * out_data, vo { field->tap = arm11->jtag_info.tap; field->num_bits = num_bits; - field->out_mask = NULL; field->in_check_mask = NULL; field->in_check_value = NULL; field->in_handler = NULL; @@ -124,7 +130,7 @@ void arm11_add_IR(arm11_common_t * arm11, u8 instr, tap_state_t state) * arm11_add_debug_SCAN_N(). * */ -static int arm11_in_handler_SCAN_N(u8 *in_value, void *priv, struct scan_field_s *field) +static void arm11_in_handler_SCAN_N(u8 *in_value) { /** \todo TODO: clarify why this isnt properly masked in jtag.c jtag_read_buffer() */ u8 v = *in_value & 0x1F; @@ -132,11 +138,10 @@ static int arm11_in_handler_SCAN_N(u8 *in_value, void *priv, struct scan_field_s if (v != 0x10) { LOG_ERROR("'arm11 target' JTAG communication error SCREG SCAN OUT 0x%02x (expected 0x10)", v); - return ERROR_FAIL; + jtag_set_error(ERROR_FAIL); } JTAG_DEBUG("SCREG SCAN OUT 0x%02x", v); - return ERROR_OK; } /** Select and write to Scan Chain Register (SCREG) @@ -171,11 +176,14 @@ void arm11_add_debug_SCAN_N(arm11_common_t * arm11, u8 chain, tap_state_t state) scan_field_t field; - arm11_setup_field(arm11, 5, &chain, NULL, &field); - - field.in_handler = arm11_in_handler_SCAN_N; + u8 tmp[1]; + arm11_setup_field(arm11, 5, &chain, &tmp, &field); arm11_add_dr_scan_vc(1, &field, state == ARM11_TAP_DEFAULT ? TAP_DRPAUSE : state); + + jtag_execute_queue_noclear(); + + arm11_in_handler_SCAN_N(tmp); } /** Write an instruction into the ITR register @@ -229,11 +237,7 @@ int arm11_read_DSCR(arm11_common_t * arm11, u32 *value) arm11_add_dr_scan_vc(1, &chain1_field, TAP_DRPAUSE); - int retval; - if ((retval=jtag_execute_queue())!=ERROR_OK) - { - return retval; - } + CHECK_RETVAL(jtag_execute_queue()); if (arm11->last_dscr != dscr) JTAG_DEBUG("DSCR = %08x (OLD %08x)", dscr, arm11->last_dscr); @@ -242,7 +246,7 @@ int arm11_read_DSCR(arm11_common_t * arm11, u32 *value) *value=dscr; - return retval; + return ERROR_OK; } /** Write the Debug Status and Control Register (DSCR) @@ -266,9 +270,7 @@ int arm11_write_DSCR(arm11_common_t * arm11, u32 dscr) arm11_add_dr_scan_vc(1, &chain1_field, TAP_DRPAUSE); - int retval; - if ((retval=jtag_execute_queue())!=ERROR_OK) - return retval; + CHECK_RETVAL(jtag_execute_queue()); JTAG_DEBUG("DSCR <= %08x (OLD %08x)", dscr, arm11->last_dscr); @@ -383,9 +385,7 @@ int arm11_run_instr_no_data(arm11_common_t * arm11, u32 * opcode, size_t count) arm11_add_debug_INST(arm11, 0, &flag, count ? TAP_IDLE : TAP_DRPAUSE); - int retval; - if ((retval=jtag_execute_queue())!=ERROR_OK) - return retval; + CHECK_RETVAL(jtag_execute_queue()); if (flag) break; @@ -447,9 +447,8 @@ int arm11_run_instr_data_to_core(arm11_common_t * arm11, u32 opcode, u32 * data, Data = *data; arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_IDLE); - int retval; - if ((retval=jtag_execute_queue())!=ERROR_OK) - return retval; + + CHECK_RETVAL(jtag_execute_queue()); JTAG_DEBUG("DTR Ready %d nRetry %d", Ready, nRetry); } @@ -465,9 +464,8 @@ int arm11_run_instr_data_to_core(arm11_common_t * arm11, u32 opcode, u32 * data, Data = 0; arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE); - int retval; - if ((retval=jtag_execute_queue())!=ERROR_OK) - return retval; + + CHECK_RETVAL(jtag_execute_queue()); JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d", Data, Ready, nRetry); } @@ -486,6 +484,8 @@ int arm11_run_instr_data_to_core(arm11_common_t * arm11, u32 opcode, u32 * data, * layer (FT2232) that is long enough to finish execution on * the core but still shorter than any manually inducible delays. * + * To disable this code, try "memwrite burst false" + * */ tap_state_t arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay[] = { @@ -550,9 +550,7 @@ int arm11_run_instr_data_to_core_noack(arm11_common_t * arm11, u32 opcode, u32 * arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE); - int retval; - if ((retval=jtag_execute_queue())!=ERROR_OK) - return retval; + CHECK_RETVAL(jtag_execute_queue()); size_t error_count = 0; @@ -625,9 +623,8 @@ int arm11_run_instr_data_from_core(arm11_common_t * arm11, u32 opcode, u32 * dat do { arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, count ? TAP_IDLE : TAP_DRPAUSE); - int retval; - if ((retval=jtag_execute_queue())!=ERROR_OK) - return retval; + + CHECK_RETVAL(jtag_execute_queue()); JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d", Data, Ready, nRetry); } @@ -728,9 +725,8 @@ int arm11_sc7_run(arm11_common_t * arm11, arm11_sc7_action_t * actions, size_t c JTAG_DEBUG("SC7 <= Address %02x Data %08x nRW %d", AddressOut, DataOut, nRW); arm11_add_dr_scan_vc(asizeof(chain7_fields), chain7_fields, TAP_DRPAUSE); - int retval; - if ((retval=jtag_execute_queue())!=ERROR_OK) - return retval; + + CHECK_RETVAL(jtag_execute_queue()); JTAG_DEBUG("SC7 => Address %02x Data %08x Ready %d", AddressIn, DataIn, Ready); } @@ -826,16 +822,13 @@ void arm11_sc7_set_vcr(arm11_common_t * arm11, u32 value) */ int arm11_read_memory_word(arm11_common_t * arm11, u32 address, u32 * result) { - int retval; arm11_run_instr_data_prepare(arm11); /* MRC p14,0,r0,c0,c5,0 (r0 = address) */ - if ((retval=arm11_run_instr_data_to_core1(arm11, 0xee100e15, address))!=ERROR_OK) - return retval; + CHECK_RETVAL(arm11_run_instr_data_to_core1(arm11, 0xee100e15, address)); /* LDC p14,c5,[R0],#4 (DTR = [r0]) */ - if ((retval=arm11_run_instr_data_from_core(arm11, 0xecb05e01, result, 1))!=ERROR_OK) - return retval; + CHECK_RETVAL(arm11_run_instr_data_from_core(arm11, 0xecb05e01, result, 1)); arm11_run_instr_data_finish(arm11);