X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=src%2Ftarget%2Farm720t.c;h=a5916aae54aec172746cfb40aa6bc8e34c2b7b5b;hb=889bd3e7163864e78ab73ed0d340b5fd1e0493e4;hp=49bdb88744463b8e2118c635c62b493388ecd7f3;hpb=6d1d58a1fc3dfd60e9cac89460b5a6e438d11efa;p=openocd

diff --git a/src/target/arm720t.c b/src/target/arm720t.c
index 49bdb887..a5916aae 100644
--- a/src/target/arm720t.c
+++ b/src/target/arm720t.c
@@ -319,7 +319,7 @@ int arm720t_arch_state(struct target_s *target)
 			"cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
 			"MMU: %s, Cache: %s",
 			 armv4_5_state_strings[armv4_5->core_state],
-			 Jim_Nvp_value2name_simple( nvp_target_debug_reason, target->debug_reason )->name ,
+			 Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name ,
 			 armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],
 			 buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
 			 buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),