X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=src%2Ftarget%2Farm9tdmi.c;h=24f3b2eb366975d7f2cf571f7faf79ca9e7dda28;hb=f1e72cf029f28a337679ca787003c54d5c1e2bde;hp=3b06b0e48d50155fca4588e86a8eef7ecf062b28;hpb=ffb51c23fdd753ada2554b8b6283533089153b46;p=openocd diff --git a/src/target/arm9tdmi.c b/src/target/arm9tdmi.c index 3b06b0e4..24f3b2eb 100644 --- a/src/target/arm9tdmi.c +++ b/src/target/arm9tdmi.c @@ -57,6 +57,8 @@ target_type_t arm9tdmi_target = .poll = arm7_9_poll, .arch_state = armv4_5_arch_state, + .target_request_data = arm7_9_target_request_data, + .halt = arm7_9_halt, .resume = arm7_9_resume, .step = arm7_9_step, @@ -64,14 +66,14 @@ target_type_t arm9tdmi_target = .assert_reset = arm7_9_assert_reset, .deassert_reset = arm7_9_deassert_reset, .soft_reset_halt = arm7_9_soft_reset_halt, - .prepare_reset_halt = arm7_9_prepare_reset_halt, .get_gdb_reg_list = armv4_5_get_gdb_reg_list, .read_memory = arm7_9_read_memory, .write_memory = arm7_9_write_memory, .bulk_write_memory = arm7_9_bulk_write_memory, - + .checksum_memory = arm7_9_checksum_memory, + .run_algorithm = armv4_5_run_algorithm, .add_breakpoint = arm7_9_add_breakpoint, @@ -82,6 +84,7 @@ target_type_t arm9tdmi_target = .register_commands = arm9tdmi_register_commands, .target_command = arm9tdmi_target_command, .init_target = arm9tdmi_init_target, + .examine = arm9tdmi_examine, .quit = arm9tdmi_quit }; @@ -98,15 +101,6 @@ arm9tdmi_vector_t arm9tdmi_vectors[] = {0, 0}, }; -int arm9tdmi_jtag_error_handler(u8 *in_value, void *priv) -{ - char *caller = priv; - - DEBUG("caller: %s", caller); - - return ERROR_JTAG_QUEUE_FAILED; -} - int arm9tdmi_examine_debug_reason(target_t *target) { /* get pointers to arch-specific information */ @@ -157,7 +151,7 @@ int arm9tdmi_examine_debug_reason(target_t *target) arm_jtag_scann(&arm7_9->jtag_info, 0x1); arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr, NULL); - jtag_add_dr_scan(3, fields, TAP_PD, NULL); + jtag_add_dr_scan(3, fields, TAP_PD); jtag_execute_queue(); fields[0].in_value = NULL; @@ -167,7 +161,7 @@ int arm9tdmi_examine_debug_reason(target_t *target) fields[2].in_value = NULL; fields[2].out_value = instructionbus; - jtag_add_dr_scan(3, fields, TAP_PD, NULL); + jtag_add_dr_scan(3, fields, TAP_PD); if (debug_reason & 0x4) if (debug_reason & 0x2) @@ -240,7 +234,7 @@ int arm9tdmi_clock_out(arm_jtag_t *jtag_info, u32 instr, u32 out, u32 *in, int s fields[2].in_handler = NULL; fields[2].in_handler_priv = NULL; - jtag_add_dr_scan(3, fields, -1, NULL); + jtag_add_dr_scan(3, fields, -1); jtag_add_runtest(0, -1); @@ -250,10 +244,10 @@ int arm9tdmi_clock_out(arm_jtag_t *jtag_info, u32 instr, u32 out, u32 *in, int s if (in) { - DEBUG("instr: 0x%8.8x, out: 0x%8.8x, in: 0x%8.8x", instr, out, *in); + LOG_DEBUG("instr: 0x%8.8x, out: 0x%8.8x, in: 0x%8.8x", instr, out, *in); } else - DEBUG("instr: 0x%8.8x, out: 0x%8.8x", instr, out); + LOG_DEBUG("instr: 0x%8.8x, out: 0x%8.8x", instr, out); } #endif @@ -300,7 +294,7 @@ int arm9tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in) fields[2].in_handler = NULL; fields[2].in_handler_priv = NULL; - jtag_add_dr_scan(3, fields, -1, NULL); + jtag_add_dr_scan(3, fields, -1); jtag_add_runtest(0, -1); @@ -310,11 +304,11 @@ int arm9tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in) if (in) { - DEBUG("in: 0x%8.8x", *in); + LOG_DEBUG("in: 0x%8.8x", *in); } else { - ERROR("BUG: called with in == NULL"); + LOG_ERROR("BUG: called with in == NULL"); } } #endif @@ -376,7 +370,7 @@ int arm9tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size, fields[2].in_handler = NULL; fields[2].in_handler_priv = NULL; - jtag_add_dr_scan(3, fields, -1, NULL); + jtag_add_dr_scan(3, fields, -1); jtag_add_runtest(0, -1); @@ -386,11 +380,11 @@ int arm9tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size, if (in) { - DEBUG("in: 0x%8.8x", *in); + LOG_DEBUG("in: 0x%8.8x", *in); } else { - ERROR("BUG: called with in == NULL"); + LOG_ERROR("BUG: called with in == NULL"); } } #endif @@ -550,7 +544,7 @@ void arm9tdmi_write_xpsr(target_t *target, u32 xpsr, int spsr) arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm_jtag_t *jtag_info = &arm7_9->jtag_info; - DEBUG("xpsr: %8.8x, spsr: %i", xpsr, spsr); + LOG_DEBUG("xpsr: %8.8x, spsr: %i", xpsr, spsr); /* MSR1 fetched */ arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr & 0xff, 0, 1, spsr), 0, NULL, 0); @@ -586,7 +580,7 @@ void arm9tdmi_write_xpsr_im8(target_t *target, u8 xpsr_im, int rot, int spsr) arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm_jtag_t *jtag_info = &arm7_9->jtag_info; - DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr); + LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr); /* MSR fetched */ arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr_im, rot, 1, spsr), 0, NULL, 0); @@ -751,7 +745,7 @@ void arm9tdmi_branch_resume(target_t *target) void arm9tdmi_branch_resume_thumb(target_t *target) { - DEBUG("-"); + LOG_DEBUG("-"); /* get pointers to arch-specific information */ armv4_5_common_t *armv4_5 = target->arch_info; @@ -849,21 +843,47 @@ void arm9tdmi_build_reg_cache(target_t *target) reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache); /* get pointers to arch-specific information */ armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; (*cache_p) = armv4_5_build_reg_cache(target, armv4_5); armv4_5->core_cache = (*cache_p); - - /* one extra register (vector catch) */ - (*cache_p)->next = embeddedice_build_reg_cache(target, arm7_9); - arm7_9->eice_cache = (*cache_p)->next; +} + +int arm9tdmi_examine(struct command_context_s *cmd_ctx, struct target_s *target) +{ + /* get pointers to arch-specific information */ + int retval; + armv4_5_common_t *armv4_5 = target->arch_info; + arm7_9_common_t *arm7_9 = armv4_5->arch_info; + if (!target->type->examined) + { + reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache); + reg_cache_t *t; + /* one extra register (vector catch) */ + t=embeddedice_build_reg_cache(target, arm7_9); + if (t==NULL) + return ERROR_FAIL; + (*cache_p) = t; + arm7_9->eice_cache = (*cache_p); + + if (arm7_9->etm_ctx) + { + arm_jtag_t *jtag_info = &arm7_9->jtag_info; + (*cache_p)->next = etm_build_reg_cache(target, jtag_info, arm7_9->etm_ctx); + arm7_9->etm_ctx->reg_cache = (*cache_p)->next; + } + target->type->examined = 1; + } + if ((retval=embeddedice_setup(target))!=ERROR_OK) + return retval; + if ((retval=arm7_9_setup(target))!=ERROR_OK) + return retval; if (arm7_9->etm_ctx) { - (*cache_p)->next->next = etm_build_reg_cache(target, jtag_info, arm7_9->etm_ctx); - arm7_9->etm_ctx->reg_cache = (*cache_p)->next->next; + if ((retval=etm_setup(target))!=ERROR_OK) + return retval; } + return ERROR_OK; } int arm9tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target) @@ -994,10 +1014,11 @@ int arm9tdmi_target_command(struct command_context_s *cmd_ctx, char *cmd, char * int chain_pos; char *variant = NULL; arm9tdmi_common_t *arm9tdmi = malloc(sizeof(arm9tdmi_common_t)); + memset(arm9tdmi, 0, sizeof(*arm9tdmi)); if (argc < 4) { - ERROR("'target arm9tdmi' requires at least one additional argument"); + LOG_ERROR("'target arm9tdmi' requires at least one additional argument"); exit(-1); }