X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=src%2Ftarget%2Farm_adi_v5.h;h=3367588f74121f7a067913ee548c31078ee36abe;hb=11a1080c00ccf0335a2ccf1a25f5a51cce75b641;hp=cdcf928a025d1370465fed2de694ba56073e4392;hpb=bd0fbef5c8819c9f58b48f02acd862d9be4d87b9;p=openocd

diff --git a/src/target/arm_adi_v5.h b/src/target/arm_adi_v5.h
index cdcf928a..3367588f 100644
--- a/src/target/arm_adi_v5.h
+++ b/src/target/arm_adi_v5.h
@@ -189,6 +189,15 @@ struct adiv5_dap {
 
 	/* true if packed transfers are supported by the MEM-AP */
 	bool packed_transfers;
+
+	/* true if unaligned memory access is not supported by the MEM-AP */
+	bool unaligned_access_bad;
+
+	/* The TI TMS470 and TMS570 series processors use a BE-32 memory ordering
+	 * despite lack of support in the ARMv7 architecture. Memory access through
+	 * the AHB-AP has strange byte ordering these processors, and we need to
+	 * swizzle appropriately. */
+	bool ti_be_32_quirks;
 };
 
 /**